Built-in testing method for delay of trigger and circuit

Abstract

The invention provides a built-in testing method for the delay of a trigger. The method comprises the following steps of: accumulating the delay of triggers to be tested, and comparing the delay with a period of a reference clock to generate a detection signal determined by the comparison; converting the detection signal, and then outputting the detection signal so that the detection signal can be directly observed from the outside of a chip; and determining the accumulated delay of the triggers to be tested through continuously changing the period of the reference clock and detecting the change of an observable signal, and finally, calculating the precise delay of a single trigger to be tested. In addition, the invention also provides a built-in testing system for the delay of the trigger. The system consists of an adjustable clock generator, a trigger delay accumulation circuit, a delay comparison circuit and an observable signal generation circuit.

Description

technical field [0001] The present invention relates to the test of digital integrated circuit, more specifically, relates to the method and circuit for the built-in test on the delay of the flip-flop on the chip. Background technique [0002] In the existing digital integrated circuit design, synchronous design is the most important design strategy. For synchronous digital circuits, the flip-flop unit is an extremely important component. The delay, power consumption, area, and reliability of the flip-flop directly determine the design difficulty, product performance, and market success rate of the integrated circuit chip. [0003] At the same time, as the market's requirements for chip functions continue to increase, the scale of digital integrated circuits continues to increase. Using an automated design process based on standard cells has become the best choice for digital integrated circuit designers. This requires accurate characteristic parameters of various standard...

AI Technical Summary

Problems solved by technology

The delay of the flip-flop not only directly affects the final frequency of the overall system, but if its precise value cannot be obtained at the early stage of design, it will seriously affect the robustness of the final chip

[0004] But today's integrated circuit manufacturing process continues to improve, and the delay of a single flip-flop has been reduced to hundreds of picoseconds (10 -12 ) magnitude, the delay parameter of the trigger has to be obtained through software simulation, although there is still a big gap between the result of software simulation and the tape-out result of the actual chip

Because first of all, it is difficult for ordinary test instruments to accurately measure the delay of the picosecond level, and secondly, the error of the delay from the inside of the chip to the test pin can be compared with the delay of the trigger to be tested

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