Deep trench filling method of superstructure

Abstract

The invention provides a deep trench filling method of a superstructure. The method comprises the steps of A. providing a deep trench to form the superstructure; B. growing a P-type epitaxial layer in the deep trench; C. depositing an oxidation layer in the middle of the P-type epitaxial layer and filing the deep trench; D. dry etching the oxidation layer in the deep trench to enable the top of the deep trench to be opened; and E. continuing to deposit the oxidation layer in the deep trench and filling the deep trench, wherein the deep trench is positioned in the N-type epitaxial layer on an N-type semiconductor substrate; and a gap is remained in the middle of the P-type epitaxial layer. Through alternately depositing the oxidation layer in the deep trench of the superstructure and etching the oxidation layer at the top of the deep trench to enable the trench opening to be fully opened, the method realizes completely seamless deep trench filling gradually, eliminates the long and narrow gap in the trench, avoids leakage phenomenon, and enables the power MOS device to meet the electrical requirement on high voltage bearing and the mechanical requirement on grinding and packaging a silicon wafer into sheets.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular, the invention relates to a deep trench filling method of a super junction structure. Background technique [0002] Power MOS devices are widely used in middle and high-end applications due to their high input impedance, low loss, fast switching speed, no secondary breakdown, wide safe operating area, good dynamic performance, easy coupling with the front electrode to achieve large current, and high conversion efficiency. Low power conversion and control field. Although power MOS devices have been amazingly improved in terms of power handling capability, their on-resistance also increases exponentially with the increase of operating voltage in the high-voltage field, making the conduction loss of power MOS devices increase with the withstand voltage increased rapidly. [0003] In order to break the silicon limit of on-resistance, increase withstand voltage, red...

AI Technical Summary

Problems solved by technology

As shown in the figure, the long and narrow slit 301 in the deep trench will cause leakage when the Cool MOS device is working, thereby reducing the electrical and mechanical properties of the device

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