Flash memory controller for solid-state hard-disk

Abstract

The invention discloses a flash memory controller for a solid-state hard-disk and belongs to the technical field of micro-electronics. The structure of the controller comprises a static random access memory (SRAM) controller, a data buffer zone, a register controller, a configuration and state register, a sub-channel controller, an error correcting code (ECC) hardware correction logic, an inspection module, an out-of-band data processing module and a NAND flash memory interface, wherein the SRAM controller is connected with and controls the data buffer zone; the SRAM controller is connected with the ECC hardware correction logic; the ECC hardware correction logic is connected with the NAND flash memory interface; the register connector is connected with and controls the configuration and state register; the configuration and state register is connected with the sub-channel controller; the configuration and state register is connected with the NAND flash memory interface; and the inspection module is connected with the out-of-band data processing module which is connected with the NAND flash memory interface. The flash memory controller has error correction capability and can support different manufacturers.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to a flash memory controller used for solid state disks. Background technique [0002] With the wide application of NAND flash memory, solid state disk (English: solid state disk, abbreviated SSD) is gradually becoming familiar to everyone. Compared with traditional mechanical hard disks, solid state disks have fast startup, fast read and write data speeds, and are not afraid of collisions and vibrations. , No noise, low power consumption and other advantages. But it also has many deficiencies, such as high cost and limited erasure times, so in order to improve the life of SSD, we will add a logical address to physical address mapping table in SSD, and adopt a wear leveling strategy at the same time. Because the cost of NAND flash memory with SLC (Single Level Cell single-level cell) structure is relatively high, flash memory with MLC (Multi-Level Cell multi-level cell) st...

AI Technical Summary

Problems solved by technology

But it also has many deficiencies, such as high cost, limited number of erasures, etc., so in order to improve the life of SSD, we will add a logical address to physical address mapping table in SSD, and adopt a wear leveling strategy

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