Control structure supporting double data rate (DDR) addressing of audio and video intellectual property (IP) cores

Abstract

The invention provides a control structure supporting the double data rate (DDR) addressing of a plurality of audio and video intellectual property (IP) cores, which comprises a physical layer and a control layer, wherein the physical layer comprises a port selection state machine, a control state machine, a clock generator, an address generator, a command generator, an automatic refresher and a data path; and the port selection state machine comprises a plurality of input ports connected with audio and video IP core signals. The control structure supports the DDR addressing of the plurality of audio and video IP core addressing, and improves the utilization rate of a DDR.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a control structure supporting multiple audio and video IP cores addressing DDR. Background technique [0002] In the solutions of consumer electronics products, many audio and video modules, such as MPEG codec, image enhancement, high-fidelity audio playback, etc., all need high-speed access to a large amount of intermediate data, and require continuous reading and writing of data without interruption. Continuously, this requires a large-capacity cache in the supported hardware system. At present, DDR is widely used because of its high storage capacity, low cost, reasonable channel bandwidth and reliable supply capacity, but it is inconvenient to use the interface. and the problem of complex control structures. [0003] DDR is a synchronous dynamic storage unit triggered by both edges of the clock. It contains several banks (Bank), and each Bank is composed of many rows...

AI Technical Summary

Problems solved by technology

[0002] In the solutions of consumer electronics products, many audio and video modules, such as MPEG codec, image enhancement, high-fidelity audio playback, etc., all need high-speed access to a large amount of intermediate data, and require continuous reading and writing of data without interruption. Continuously, this requires a large-capacity cache in the supported hardware system. At present, DDR is widely used because of its high storage capacity, low cost, reasonable channel bandwidth and reliable supply capacity, but it is inconvenient to use the interface. and the problem of complex control structures

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