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Apparatus for providing SRAM and CAM bit cell

A technology of bit unit and storage unit, applied in electrical components, static memory, instruments, etc., to achieve the effect of improving access speed, reducing standby power consumption, and improving Vcc

Active Publication Date: 2013-06-19
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The use of smaller devices results in large variations in device performance

Method used

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  • Apparatus for providing SRAM and CAM bit cell
  • Apparatus for providing SRAM and CAM bit cell
  • Apparatus for providing SRAM and CAM bit cell

Examples

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Embodiment Construction

[0069] The method of making and using the preferred embodiments of the present invention will be described in detail as follows. Many of the inventive application concepts provided by the present invention can be embodied in a wide variety of specific contexts. The specific embodiments discussed below are merely illustrative of specific ways to make and use the invention and do not limit the scope of the invention.

[0070] Figure 4 An embodiment of the present invention shows a circuit diagram of an 8T SRAM bit cell 40 that incorporates the features of the double gate oxide layer of the present invention. exist Figure 4 The middle 6T storage unit part 42 has two such as Figure 1-Figure 3 The PMOS pull-up transistors PU1 and PU2 shown, and four such as Figure 1-Figure 3 NMOS transistors PG1, PG2, PD1 and PD2 are shown. In this invention, thick gate dielectric layers are used to form the four NMOS transistors. With the use of a thick gate dielectric layer, the standby...

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PUM

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Abstract

The invention provides circuits and methods for providing an SRAM and CAM bit cell. In one embodiment, a bit cell portion with thicker gate oxides in the storage cell transistors, and thinner gate oxides in a read port section having transistors are disclosed. The use of the thick gate oxides in the storage cell transistors provides a stable storage of data and lower standby leakage current. The use of the thinner gate oxides in the read port transistors provides fast read accesses and allows a lower Vcc,min in the read port. The methods used to form the dual gate oxide thickness SRAM cells have process steps compatible with the existing semiconductor manufacturing processes. Embodiments using high k gate dielectrics, dual gate dielectric materials in a single bit cell, and using finFET and planar devices in a bit cell are described. Methods for forming the structures are disclosed.

Description

technical field [0001] The present invention relates to a bit cell structure of Static Random Access Memory (SRAM) and a method of providing a bit cell with improved standby leakage current (Isb) to obtain improved standby operation, improved Vcc, min, Reduced supply levels have minimum power, high speed read times. [0002] The bitcell includes a new layout and multiple thickness gate oxides in the cell transistors. The use of the present invention provides the advantage of utilizing the SRAM in an integrated circuit having a logic circuit or a user-specified circuit. In addition to SRAM arrays of SRAM bit cells, SRAM cells also have improved stability and provide reliable operation in a wide range of conditions. Methods of fabricating SRAM bit cells incorporating features of the present invention may be compatible with existing state of the art and planned semiconductor processes. Background technique [0003] A general requirement today for electronic circuits, especia...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11H01L29/10H10B10/00
CPCG11C15/04G11C11/412
Inventor 王屏薇杨昌达米玉杰
Owner TAIWAN SEMICON MFG CO LTD
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