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Restart scheduling method of failure look-ahead threads

A scheduling method and thread technology, applied in the computer field, can solve problems that hinder the development of high-performance computing, high power consumption and heat dissipation, and difficulty in significantly improving performance, and achieve the effect of reducing the cost of thread restart and improving efficiency

Inactive Publication Date: 2013-01-09
SHANGHAI UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] At present, it is difficult for high-performance processors to significantly improve their performance only by increasing the main frequency of the processor and complex instruction pipeline technology, and doing so will also cause difficult problems such as high power consumption and heat dissipation. Therefore, single-chip multi-core processors (Chip Multi -Processors, CMP) technology has become one of the key technologies to improve processor performance
Although CMP technology has a good effect on parallel execution of multi-threads, most programs are still serial programs. How to apply these serial programs to the CMP platform and make them run efficiently has always hindered high-end The evolution of performance computing
However, the results inferred by the forward-looking technology are not always correct, which means that some threads will inevitably fail to look forward

Method used

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  • Restart scheduling method of failure look-ahead threads

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Comparison scheme
Effect test

Embodiment 1

[0023] Embodiment 1: This forward-looking invalidation thread restart scheduling method, the specific operation steps are as follows:

[0024] A. Detect invalid look-ahead threads;

[0025] B. Calculate the resources occupied by each forward-looking invalid thread, denoted as M(i), i∈[0,n], n is the total number of all invalid threads;

[0026] C. Calculate the number of successor threads of each forward-looking failure thread, denoted as N(i), i∈[0,n], n is the total number of all failure threads;

[0027] D, determine the size of the sum of M(i) in step B and the total number M of existing idle resources, and select the execution thread;

[0028] E. Continue to return to step D for the remaining threads until all invalidated threads are re-executed;

[0029] F. Thread scheduling execution ends.

Embodiment 2

[0030] Embodiment 2: This embodiment is basically the same as Embodiment 1, and the special features are as follows:

[0031] The execution sequence of the step D thread directly depends on the parameters in the steps B and C, and the operation steps are as follows:

[0032] D1. When the sum of M(i) in step B is less than the total number M of existing free resources, go to step D11; when the sum of M(i) in step B is greater than the total number M of existing free resources, go to step D1. to step D21;

[0033] D11, judging whether the restart thread is a predecessor and successor thread each other, if so, first execute the predecessor thread and go to step D11; otherwise go to step D12;

[0034] D12, compare the resources M(i) occupied by restarting threads, and execute the threads with smaller M(i) first; go to step F;

[0035] D21, judging whether the restart thread is a predecessor and successor thread each other, if yes, first execute the predecessor thread and go to s...

Embodiment 3

[0037] Embodiment 3: The application environment of the solution described in this embodiment is a forward-looking thread parallel execution environment for multi-core processors. This embodiment does not limit the multi-core processor architecture and thread scheduling method in the application environment of the technical solution.

[0038] refer to figure 1 , the operation steps of this forward-looking failure thread restart scheduling method are as follows:

[0039] Step A (101), detecting invalid look-ahead threads.

[0040] Step B (102), calculating the resources M(i) occupied by each lookahead invalidated thread.

[0041] Step C (103), calculating the number N(i) of successor threads of each look-ahead invalidation thread.

[0042] Step D1 (104), judging whether the sum of M(i) is greater than the total number M of existing idle resources.

[0043] Step D11 (105), judging whether the restart thread is the predecessor thread or the successor thread of each other.

[...

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Abstract

The invention aims to provide a restart scheduling method of failure look-ahead threads. The method decides a restart exertion sequence of failure look-ahead threads according to the mutual relation between look-ahead threads and occupied resources. The method comprises the following steps of: detecting failure look-ahead threads; calculating resources and successor thread of a failure thread; judging priority execution levels of the failure thread and successor thread; and restarting the threads. The invention not only can preferably restart a thread with less resource need, but also can consider the conditions that the thread is the precursor thread or the successor thread of another thread, reduce the thread restart cost in case look-ahead failure and improve the thread restart efficiency.

Description

technical field [0001] The invention relates to the field of computers, and proposes a method for restarting scheduling of forward-looking invalid threads. Background technique [0002] At present, it is difficult for high-performance processors to significantly improve their performance only by increasing the main frequency of the processor and complex instruction pipeline technology, and doing so will also cause difficult problems such as high power consumption and heat dissipation. Therefore, single-chip multi-core processors (Chip Multi -Processors, CMP) technology has become one of the key technologies to improve processor performance. Although CMP technology has a good effect on parallel execution of multithreading, most of the programs are still serial programs. How to apply these serial programs to the CMP platform and make them run efficiently has always hindered high-end The evolution of performance computing. [0003] Parallel technology based on Thread-Level Sp...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/48
Inventor 赵文江杨洪斌吴悦徐振坤刘清华
Owner SHANGHAI UNIV
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