Semiconductor device and method for manufacturing the same

Abstract

The invention discloses a semiconductor device and a method for manufacturing the same. The method for manufacturing a semiconductor device includes the steps of: (a) forming a gate electrode on a substrate, forming source / drain regions and a channel forming region in the substrate, and forming on the source / drain regions a first interlayer insulating layer equal in height to the gate electrode; (b) forming in the first interlayer insulating layer groove-shaped first contact portions connected to the source / drain regions; (c) forming a second interlayer insulating layer on a whole surface; (d) forming hole-shaped second contact portions in portions of the second interlayer insulating layer on the first contact portion; and (e) forming on the second interlayer insulating layer wires connected to the second contact portions.

Description

[0001] Cross References to Related Applications [0002] This application contains subject matter related to that disclosed in Japanese Priority Patent Application JP2009-190645 filed with Japan Patent Office on Aug. 20, 2009, the entire content of which is hereby incorporated by reference incorporated into this article. technical field [0003] The invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background technique [0004] Recently, the trend toward miniaturization of components in semiconductor devices and semiconductor integrated circuits has caused a problem of increasing contact resistance. Meanwhile, many attempts have been made to improve the characteristics of circuit transistors using a technique aimed at increasing carrier mobility by applying stress to a channel formation region with a stressing material. [0005] Regarding the problem of increased contact resistance, for example, C.Auth et al. in "45nm High...

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Problems solved by technology

[0008] In the technique disclosed in Japanese Patent Application JP-A-2001-291770, since the contact plug and the control electrode are separated only by the first side wall spacer, there is a high possibility of a short circuit between the contact plug and the control electrode

In addition, since the contact plug is formed in the form of a side wall, position misregistration is likely to occur between the contact plug and the metal plug connected thereto.

In addition, when the width of the element isolation region is made narrow due to the miniaturization of the circuit, since the distance between the metal plug and the metal plug connected to the contact plug disposed near the element isolation region is shortened, there is a high possibility of a gap between the metal plugs. short circuit

For this reason, the technology disclosed in the Japanese patent application JP-A-2001-291770 is not suitable for the miniaturization process, and it is difficult to reduce the circuit area by this technology

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