Manufacturing method of semiconductor device

Abstract

The invention discloses a manufacturing method of a semiconductor device, which comprises the steps of: providing a wafer, wherein a wafer surface comprises a conductive layer and an insulating layer which is positioned above the conductive layer; coating a photomask layer on the surface of the insulating layer; patterning the photomask layer in the center area of the wafer, with the photomask layer on the edge area of the wafer unpatterned; exposing a partial insulating layer in the center area on the wafer; completely covering the insulating layer of the edge area of the wafer; etching the exposed insulating layer; and consequently forming a through hole for exposing the conductive layer in the insulating layer. The defect of the surface of the wafer, caused by chips of conductive impurities, is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a semiconductor device. Background technique [0002] The manufacture of semiconductor integrated circuits is an extremely complex process, the purpose of which is to reduce the various electronic components and circuits required for a specific circuit on a small-area wafer. Wherein, each component must be electrically connected by an appropriate interconnection wire, so as to exert the desired function. [0003] As the production of integrated circuits develops toward ultra-large-scale integrated circuits (ULSI), the internal circuit density is increasing. As the number of components contained in the chip continues to increase, the available space for surface wiring is actually reduced. The solution to this problem is to adopt a multi-layer metal wire design, and use a multi-layer connection in which a multi-layer insulating layer a...

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Problems solved by technology

[0007] However, for the test of the wafer after the contact hole is formed in the 65nm process by the above method, it is found that a lot of conductive impurity debris is distributed on the wafer, thereby forming defects on the wafer surface

figure 1 For the test pattern of the wafer after the contact hole is formed by the method of the prior art, from figure 1 It can be seen that using the existing method, there are defects caused by conductive impurities on the surface of the wafer.

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