Glitch-eliminating programmable counter

Abstract

The invention discloses a glitch-eliminating programmable counter, which comprises an asynchronous counter main body circuit, a programmable logic circuit, an reset pulse generation circuit and a counter output generation circuit, wherein the asynchronous counter main body circuit is provided with N-bit frequency division output end (Q0...QN-1), a programmable input end P and a trigger D; the programmable logic circuit is divided into a programmable part and a non-programmable part, the programmable part adopts a NAND logic, while the non-programmable part adopts a NOR logic; the reset pulse generation circuit is provided with two input ends R0 and S0 and three output ends; and the counter output generation circuit is provided with two input ends R1 and S1 and one outlet end. The glitch-eliminating programmable counter has the characteristics of simple design, novel circuit structure, high glitch-eliminating capability, easy realization and the like.

Description

technical field [0001] The invention relates to a burr elimination programmable counter, which is mainly applied to a programmable frequency divider circuit in a radio frequency phase-locked loop. Background technique [0002] In the RF phase-locked loop circuit, the programmable frequency divider circuit is the main module, which provides a variable frequency division ratio for the entire loop, and realizes the precise locking of the phase-locked loop at different frequency points. Programmable counters are the primary way to implement programmable frequency dividers. By inputting different frequency division ratio control words, the programmable frequency divider outputs different frequency division ratios. [0003] In actual circuit design, the programmable counter in the programmable frequency division circuit is realized by digital logic, which can be divided into two parts: the counter main circuit and the programmable logic circuit. The main circuit of the counter i...

AI Technical Summary

Problems solved by technology

[0004] In order to eliminate the output burr caused by the competition-adventure of the combinational logic circuit, the general method is to introduce a D flip-flop to synchronize the output of the programmable logic circuit. However, this method also has the danger of miscounting. When the clock rising edge of the flip-flop arrives, the glitch will also be transmitted to the output terminal, causing the count output to be wrong

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