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QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) code decoder and implementation method thereof

An implementation method and decoder technology, applied in the field of digital communication

Active Publication Date: 2010-12-15
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0044] The technical problem to be solved by the present invention is: on the basis of reducing the hardware implementation complexity of the QC-LDPC code decoder, optimize the allocation of storage resources, reduce the number of RAM units by merging, improve the use efficiency of RAM units, and realize logic Flexible trade-off between resources, storage resources, routing resources and system throughput

Method used

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  • QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) code decoder and implementation method thereof

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Embodiment

[0140] In this embodiment, the combination factor F 1 =F 2 =2, and the technical solution of the present invention is described by taking the construction of XRAM-C according to CSMG-H as an example.

[0141] Such as Figure 8 As shown, it represents a simple H matrix with a quasi-cyclic structure, which is not an H matrix of an actual QC-LDPC code, and is only used for the QC-LDPC code decoder provided by the present invention and its implementation method The specific implementation will be described in detail. The H matrix is ​​composed of 4 row vectors and 6 column vectors, in which the striped block is CSM, and the colorless block is ZSM, and the CSM is numbered i-j according to its row and column positions, i represents the row, and j represents the column.

[0142] Multiplexing group construction steps: first construct HSG, construct the 1st and 2nd row vectors into HSG1, and the 3rd and 4th row vectors into HSG2; then build VSG, construct the 1st and 2nd column vect...

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Abstract

The invention provides a QC-LDPC code decoder and an implementation method thereof. The decoder comprises an HPU (Hydraulic Pumping Unit) array, a VPU (Visual Processing Unit) array, an ARAM-C array, a CARM-C array, a multiplexing unit and a control unit. The decoder and the implementation method thereof provided by the invention completely utilize characteristic of a QC-LDPC code semi-parallel decoder structure, develop optimizing potentials, carry out optimizing configuration on storage resources on the basis of reducing hardware implementation complexity by introducing a horizontal and a vertical multiplying multiplexing computing units, obviously improve the utilization efficiency of an RAM unit during hardware implementation, reduce quantity of required RAM units and reduce logic resources occupied by the multiplexing unit through RAM block combination, simultaneously optimize wiring resources required by hardware implementation effectively, and can flexibly exchange among logic resources, storage sources, wiring resources and throughput rates.

Description

technical field [0001] The invention relates to the technical field of digital communication, in particular to a QC-LDPC code decoder and an implementation method thereof. Background technique [0002] LDPC code (Low Density Parity Check Code, Low Density Parity Check Code) is a kind of special linear block code based on sparse check matrix proposed by Robert G. Gallager in 1962. It is usually described by a parity check matrix H, and the null space of the parity check matrix H is the codeword of the LDPC code. Its main feature is that the parity check matrix is ​​sparse. LDPC code not only has excellent performance close to the Shannon limit, but also has low decoding complexity and flexible structure. It is a research hotspot in the field of channel coding in recent years. It has been widely used in deep space communication, optical fiber communication, ground and satellite digital multimedia broadcasting. and other fields. LDPC code has become a strong competitor for th...

Claims

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Application Information

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IPC IPC(8): H04L1/00H03M13/11
Inventor 王昭诚刘在爽杨知行彭克武张超
Owner TSINGHUA UNIV
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