Method for quickly extracting critical area of layout

Abstract

The invention discloses a method for quickly extracting the critical area of a layout, which includes the following steps that: layout information is extracted; a blocked ordered multi-level indexed table is established; the defects of the production technique are simulated at random, and the affection is statistically analyzed; and the blocked ordered multi-level indexed table is utilized to calculate the critical area. By utilizing the method which first classifies basic pattern units of the integrated circuit layout and then hierarchically traverses a layout tree to extract all the patterns superposed with defective polygons, the invention can quickly extract all the patterns superposed with defective polygons in a layout tree with great depth and extension within an effective time andspace range and calculate the critical area of the layout, and is used for directing the practical integrated circuit production to increase the yield.

Description

technical field [0001] The invention relates to the field of computer-aided design of integrated circuits, in particular to a method for rapidly extracting the key area of ​​an integrated circuit layout. Background technique [0002] The manufacturing efficiency of integrated circuits depends entirely on its production yield. Especially under advanced technology (below 150nm), how to improve the yield is very important. [0003] At present, people have done a lot of research on the yield rate. Based on the concept of critical area, many models that can be used to predict the yield rate of integrated circuit manufacturing have been proposed and simulated by computer. Among these methods, the Monte Carlo (MONTE CARLO) method is widely adopted because of its good effect and fast speed. As the publication number is CN101183399A, the Chinese patent titled "A Method for Analyzing and Improving the Yield of a Semiconductor Production Line" discloses A method for analyzing and impr...

AI Technical Summary

Problems solved by technology

In the computer field, integrated circuit layout data is represented as a tree structure. Since the layout of integrated circuits is very different, the represented layout data is usually an unordered tree, and the mature algorithm of a special tree cannot be used to complete the search function.

Moreover, when establishing the yield prediction model, in order to verify whether the simulated defect pattern causes failure, it is necessary to traverse the layout tree to extract all the patterns that coincide with the defect polygon. However, as the size of the layout process decreases, the area continues to increase. The increase of the layout level, the expansion of the scale and the increase of the complexity have caused the calculation of the basic graphic unit of the integrated circuit to be in the order of billions, so the depth and breadth of the layout tree are also very large. This step is done within the spatial extent

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