High pressure P-shaped metal oxide semiconductor tube of silicon-on-insulator

Abstract

The invention provides a high pressure P-shaped metal oxide semiconductor tube which is used for silicon-on-insulator, comprising a semiconductor substrate, wherein a buried oxide layer is arranged on the semiconductor substrate; the buried oxide layer is provided with an isolation deep groove which is constituted by a left oxide layer, a right oxide layer and a polysilicon layer which is arranged between the left oxide layer and the right oxide layer; the left and right sides of the isolation deep groove are both high pressure P-shaped metal oxide semiconductor tubes of silicon-on-insulator with common structures; an N-shaped contact area of the transistors at the right side of the deep groove is connected with the polysilicon layer in the middle of the deep groove through a layer of polysilicon on the surface; and the right oxide layer of the deep groove clings closely with the N-shaped contact area of the transistors at the right side of the deep groove. The isolation groove structure not only can effectively prevent the overburning of the high pressure P-shaped metal oxide semiconductor tube of silicon-on-insulator at the right side of the deep groove under the condition of breakdown, but also can effectively reduce chip area and improve integration level.

Description

technical field [0001] The invention belongs to the field of power semiconductor devices, and more specifically relates to a high-voltage P-type metal oxide semiconductor tube of silicon-on-insulator suitable for high-voltage applications. Background technique [0002] Power semiconductor devices are the basic electronic components for energy control and conversion in power electronic systems. The continuous development of power electronics technology has opened up a wide range of application fields for semiconductor power devices, and the characteristics of semiconductor power devices such as on-resistance and breakdown voltage determine The basic performance of the power electronic system, such as efficiency and power consumption. Modern power electronic devices and related products represented by lateral double-diffused metal-oxide-semiconductor transistors are playing an increasingly important role in industries, energy, transportation, and other occasions that use elect...

AI Technical Summary

Problems solved by technology

[0003] However, it is precisely because silicon-on-insulator lateral double-diffused metal-oxide-semiconductor transistors are widely used in high-voltage applications, so the requirements for the isolation technology between semiconductor transistors are more stringent. The isolation between them, but also to minimize the integration, reduce the use of chip area

[0004] In the past, people used PN junctions to isolate silicon-on-insulator lateral double-diffused metal-oxide-semiconductor transistors. Although this method is compatible with the process and is simple and easy, this isolation needs to increase the area of ​​the PN junction to improve the resistance to punch-through. Wearability, so the chip area consumed is relatively large, which is not conducive to effective chip integration

[0005] Later, people proposed deep trench isolation technology, that is, using deep trenches to effectively isolate the lateral double-diffused metal-oxide-semiconductor transistors of silicon-on-insulator, because the oxide layer in the deep trench isolation structure can bear a large withstand voltage , so the isolation between transistors can be completed in a small chip area, but with the continuous advancement of research on deep trench isolation technology, people have gradually found that the silicon layer outside the edge of the oxide layer near the high-voltage power supply in the deep trench isolation structure Breakdown is prone to occur, which will cause the transistor to burn out, so it is necessary to separate the deep trench isolation structure from the high-voltage power supply, which obviously increases the consumption of chip area

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