Verification environment system and construction method thereof

Abstract

The embodiment of the invention discloses a verification environment system and a construction method thereof. The construction method of a verification environment comprises the following steps: acquiring port information required by the construction of the verification environment and generating a layered structure of the verification environment; and constructing, layer by layer, parts required by the layered structure of the verification environment in a direction opposite to configured data stream according to port signals from a tested designed top layer. The verification environment system and the construction method thereof can realize effective reuse and fast construction of the verification environment.

Description

technical field [0001] The invention relates to the technical field of verification, in particular to a verification environment system and a construction method thereof. Background technique [0002] Verification is an indispensable process in the chip product development process to prove whether the design function is realized and implemented correctly. In order to better complete the verification, the verification personnel need to often build an appropriate and efficient verification environment around the design. With the rapid development of the field of chip verification in the past 20 years, there are various methods to build the verification environment. At present, it is more commonly used in the industry to build around the simulation top layer, which is to generate a verification environment that just satisfies the design under test (DUT, DesignUnder Test) based on the simulation top layer information, which has the advantages of simplicity and flexibility. [0...

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Problems solved by technology

[0010] 5. There is no unified construction main line and automated construction ideas, and it needs to rely too much on the manual editing of verifiers, but it is more convenient to modify later

With the rapid expansion of the existing chip verification scale, the continuous reduction of its development cycle and the continuous improvement of verification quality requirements, the method of building around the top layer of simulation cannot fully satisfy us to quickly build a verification environment that is appropriate to product characteristics.

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