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Electrostatic discharge protection pattern for high voltage applications

By using separate N+S/D island implant patterning and oxide doped isolation areas in semiconductor devices, the problem of insufficient ESD protection in high-voltage environments is solved, achieving higher current limit and device durability, and avoiding equipment Premature failure and safety risks.

Inactive Publication Date: 2009-12-09
TAIWAN SEMICON MFG CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The zero-gap N + The disadvantage of S / D implants and similar configurations is that they do not typically provide good and acceptable ESD protection for high voltage applications

Method used

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  • Electrostatic discharge protection pattern for high voltage applications
  • Electrostatic discharge protection pattern for high voltage applications
  • Electrostatic discharge protection pattern for high voltage applications

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Embodiment Construction

[0029] The making and utilization of presently preferred embodiments are described in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific situations. The specific embodiments discussed are only intended to illustrate the making and use of the present invention in specific ways, and are not intended to limit the scope of the present invention.

[0030] now refer to figure 1 , shows a gap with zero N + Plan view of transistor group 10 with doped S / D regions 103 . The transistor group 10 includes S / D contact holes 100 and 101 , and a gate 102 . By setting N at the S / D contact hole 100+ The doped region provides ESD protection for the transistor group 10 . Although the zero gap N + Doped region 103 reduces breakdown that occurs at high voltage operation, but lateral and other breakdown current leakage associated with ESD still continues to be experienced in t...

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Abstract

Electrostatic discharge (ESD) protection in high voltage semiconductor devices is disclosed that provides enhanced current isolation between transistor drains or sources by creating an isolation island surrounding the drains or sources. This isolation island can be a higher-doped region within which the drain / source lies. The junction between the higher doping of this island region and the surrounding substrates operates to limit the amount of current that passes through the drain / source. Additionally, oxide features may be used to create an island surrounding the drain / source contact. Again, this isolating effect makes the amount of current passing through the device more uniform, which protects the device from damage due to an ESD event.

Description

technical field [0001] The present invention generally relates to semiconductor device technology, and in particular, relates to a high-voltage electrostatic discharge (ESD) protection pattern. Background technique [0002] Computer microchips have permeated every aspect of modern life. From the single microchip embedded in a small device to the multitude of microchips that make our airplanes fly and our cars run, we are increasingly dependent on semiconductor device technology. Considering all the important operations controlled by semiconductor devices, one of the most important topics is the endurance and reliability of these devices. A prerequisite element in semiconductor device design is protecting the device from electrostatic discharge (ESD). ESD refers to the transfer of charge between objects of different potentials. ESD is a serious problem in solid state electronics. Integrated circuits are made of semiconductor materials such as silicon or insulating materia...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02H01L21/82
CPCH01L29/0873H01L29/0878H01L29/0653H01L29/7816H01L29/0696H01L29/42368H10D62/116H10D62/156H10D62/157H10D62/127H10D64/516H10D30/65
Inventor 李建兴陈遂泓蔡泳田欧东尼
Owner TAIWAN SEMICON MFG CO LTD
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