Device, system and method for exception processing of embedded device

Abstract

The embodiment of the invention provides a device, a system and a method for exception processing of an embedded device. The device comprises a configuration information acquisition module, a storage module and a configuration module, wherein the configuration information acquisition module is used for acquiring initial configuration information of an operation sub module; the storage module is used for storing the initial configuration information of the operation sub module; and the configuration module is used for newly configuring the operation sub module according to the stored initial configuration information when the exception of the operation sub module is detected. The method comprises the following steps: acquiring and storing the initial configuration information of the operation sub module; and newly configuring the operation sub module according to the stored initial configuration information when the exception of the operation sub module is detected. The embodiment of the invention also provides the method for exception processing of the embedded device. When the exception happens, the system can be automatically recovered, and the service operation quality is improved.

Description

technical field [0001] The invention relates to the field of embedded technology, in particular to an exception handling device, system and method for embedded equipment. Background technique [0002] Field Programmable Gate Array (Field Programmable Gate Array, hereinafter referred to as: FPGA) has reprogrammable characteristics and parallel processing capabilities, can replace DSP to undertake the task of data processing, and has great significance for bit-level processing in the field of communication technology. The advantages have been widely used in the field of communication technology and promote the development of communication technology. [0003] In scenarios where FPGAs are used in communication processing, there are often abnormalities in the communication link, such as receiving data packets beyond the fault-tolerant processing capability, and the processed link capacity exceeds the preset design capacity of the link. It may cause the FPGA subsystem processing...

AI Technical Summary

Problems solved by technology

[0005] The inventor finds in the process of realizing the present invention that there are at least the following technical problems in the prior art: in the running process of the existing FPGA system, when an exception occurs, the exception handling is performed by recompiling the version, which will cause the business to run on the FPGA. Interruption, reducing the quality of business operations

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