Parameter computation method of RFCMOS model with expandability

Abstract

The invention discloses a parameter calculation method for RFCMOS models of expansibility. The model adds a sub circuit based on the MOS field transistor of BSIM3V3 model, wherein the sub circuit comprises a parasitic resistance of grid electrode, a parasitic resistance of source electrode, a parasitic resistance of drain electrode and a substrate network. The substrate network comprises a parasitic diode between the source electrode and the substrate, a parasitic diode between the drain electrode and the substrate, a coupling resistance between the source electrode and the substrate, a coupling resistance between the drain electrode and the substrate, and a coupling resistance of the substrate. The parasitic resistance of the grid electrode and the components forming the substrate network are calculated from variable parameters which at least comprise one of transistor channel length, channel width and the number of parallel grid electrodes. The parameter calculation method improves model precision, effectively realizes model expansibility and effectively reduces the design cost of radio frequency circuits.

Description

technical field The present invention relates to an RFCMOS (Radio Frequency CMOS) model. Background technique With the continuous development of CMOS technology, deep submicron CMOS devices have the characteristics of high-frequency signal transmission and low noise, so they are more and more used in radio frequency (RF) circuit design and widely used in the field of wireless communication. In RFCMOS circuit design, only by establishing an accurate RFCMOS model can the performance of RFCMOS devices be accurately simulated during circuit simulation, thereby saving the RFCMOS circuit design cycle. The RFCMOS model requires more emphasis on describing high-frequency performance such as nonlinearity, high-frequency noise, and non-quasi-static effects of RFCMOS devices on the basis of including all low-frequency characteristics. So far, there is no standard RFCMOS model in the industry, and RFCMOS devices are usually simulated by adding branch circuits based on the BSIM3v3 mod...

AI Technical Summary

Problems solved by technology

Due to the particularity of RFCMOS layout design, most of the RFCMOS models shown in Figure 1 are limited to simulating RFCMOS devices of a certain size or a small range of sizes, and the scalability is poor.

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