Time synchronization method and system for multi-core system

Abstract

The invention discloses a multi-core system time synchronization method and a system thereof; the time synchronization method comprises the following steps: A, establishing at least a clock synchronization domain, and distributing the cores respectively into each lock synchronization domain; B, selecting the core with the minimum load as the master clock synchronization source in each clock synchronous domain, and taking the clock synchronization domain having the master clock synchronization source with the minimum load among all the master clock synchronization sources as the master clock synchronization domain, and taking the other clock synchronization domains as the slave clock synchronization domains; C, after the master clock synchronization domain sends synchronization error detection information to each slave clock synchronization domain, calculating the time deviation value between each slave clock synchronization domain and the master clock synchronization domain; D, when the time deviation value is greater than the permitted deviation value, the master clock synchronization domain calculates the time adjustment quantity of each slave clock synchronization domain and releases the time adjustment quantity to each slave clock synchronization domain, then each slave clock synchronization domain makes adjustment based on the corresponding time adjustment quantity. The invention effectively solves the time synchronization problem of the multi-core system.

Description

technical field [0001] The invention relates to the field of multi-core processors, in particular to a time synchronization method and system for a multi-core system. Background technique [0002] In a single-core embedded processor system, usually only a single embedded operating system can be run, and during system operation, the most critical system clock interrupt is through converting the time interval of the scheduled interrupt into a specific value. When the time interval value is high, submit the timing interrupt to the kernel and the processor will automatically reload the counter to complete it; considering that the interval of the timing interrupt should not be too frequent, the system usually sets the interval of the system timing interrupt to 10ms ~ 100ms, and each time it occurs When the clock is interrupted, the system enters the timing interrupt service program, accumulates the ticks of the system (clock tick, which is the relative time unit of the system, co...

AI Technical Summary

Problems solved by technology

When a multi-core system runs multiple embedded operating systems, for example, each core independently runs embedded operating systems such as vxWorks and Linux, such as figure 1 As shown, each core 10 in the multi-core system 20 independently completes the system clock counting function through the clock interrupt 30. Due to reasons such as unbalanced running load of each core, the system clock tick of the embedded operating system running on each core cannot be kept in sync. , on the contrary, as the system running time increases, the system clock ticks of different cores will have a large deviation. Since the upper layer software timer is generally designed based on the system clock tick, this deviation will seriously affect the different cores when the deviation reaches a certain level. Accuracy and synchronization of upper layer application software timers

For example, assuming that each clock interrupt tick of the operating system is 10ms, if the operating system on multiple cores also sets a timer with a duration of 10,000 ticks, the clock interrupt on the core will be lost due to unbalanced load of a certain core, resulting in tick produces deviation

When the cumulative deviation of the clock ticks of different cores reaches 5 ticks or 50ms, this is intolerable in some time-sensitive applications

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