Design method of asynchronous block cipher algorithm coprocessor

Abstract

The invention discloses a method for designing an asynchronous block cipher algorithm coprocessor, wherein the technical problem which should be solved is to provide the method for designing the asynchronous block cipher algorithm coprocessor. The technical scheme comprises: taking each round of iteration in the block cipher algorithm as an independent submodule, adopting HDL to design each submodule, carrying out logic synthesis to each submodule, obtaining a static monorail net list, transforming the static monorail net list into a composite logic net list which is composed of two inputs which are complementary and doors and / or the doors, carrying out delay matching to each submodule, adding a delay matching module with same delay with the submodule, guaranteeing that the delays of signal input to signal output of each submodule are same, guaranteeing that the input reach time with the doors and / or the doors is same, connecting each submodule in turn, obtaining a complete net list, carrying out rear placement and routing, and obtaining a GDS layout. The coprocessor which is designed through adopting the method has higher power consumption attack resisting and protection ability and simultaneously has high operation performance and low power consumption features.

Description

technical field [0001] The invention relates to a design method of a microprocessor, in particular to a design method of a cryptographic algorithm co-processor. Background technique [0002] The security of cryptographic algorithms includes two aspects, one is the security in the mathematical sense of cryptographic algorithms, and the other is the security in the implementation of cryptographic algorithms. Traditional cryptanalysis is a cracking method aimed at the cryptographic algorithm itself, such as differential and linear cryptanalysis. Conventional cryptanalysis and brute force cracking are ineffective for existing widely used cryptographic algorithms. The power consumption attack is an effective method to crack the key by using the weak link in the specific implementation of the cryptographic algorithm, and it is the attack method with the highest security threat in the side-channel attack. Because there is a statistical correlation between the private key in the se...

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Problems solved by technology

However, compared with the above constant power consumption logic units such as logic units based on sensitive amplifiers, the constant power consumption characteristics of asynchronous circuits are relatively poor, that is, the protection ability is relatively low

Compared with synchronous circuits, the most significant advantage of asynchronous circuits lies in their low power consumption. The low power consumption design and implementation technology based on asynchronous circuits is also the frontier research content in the field of integrated circuits; but asynchronous circuits do not have computing performance and chip Advantages in terms of area

In addition, the realization of asynchronous circuits is relatively difficult, and there is a lack of mature auxiliary design tools

At present, there is no public report on the asynchronous block cipher algorithm coprocessor that adopts asynchronous circuit design to realize high anti-power attack protection ability, high computing performance and low power consumption.

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