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Comparator and A/D converter

A technology of comparators and comparison results, applied in analog/digital conversion, code conversion, instruments, etc., to achieve the effects of expanding frequency, improving comparison accuracy, and overcoming offset

Inactive Publication Date: 2009-01-14
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, the NMOS transistors m2a and m2b are in the cut-off state (OFF), the current path is disconnected, and the power consumption is 0

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0075] figure 1 It is a figure which shows an example of the structure of the dynamic comparator 100 of this Embodiment 1.

[0076] exist figure 1 Among them, the comparator 100 includes: an input transistor part 10 including NMOS transistors m11, m12, m21, m22, a positive feedback part (cross-coupled inverting latch part) 11 including NMOS transistors m1a, m1b and PMOS transistors m3a, m3b, The output terminal QB is connected to the gate terminals of m1a and m3a of the positive feedback part 11 and the drain terminal of m3b, and the gate terminals of the transistors m1b and m3b of the positive feedback part 11 are connected to the drain terminal of the transistor m3a. Output terminal Q.

[0077] In addition, in figure 1 In, between the drain terminal of the NMOS transistor m1a and the drain terminal of the PMOS transistor m3a is connected the NMOS transistor m2a which is synchronized with the clock signal CLK and used as a switch, between the drain terminal of the NMOS ...

Embodiment approach 2

[0106] Figure 4 It is a figure which shows an example of the structure of the dynamic comparator 400 of Embodiment 1. The comparator 400 includes: an input transistor section including NMOS transistors m11, m12, m21, m22, a positive feedback section (cross-coupled inverting latch section) including NMOS transistors m1a, m1b, and PMOS transistors m3a, m3b. The gate terminals of the transistors m1a and m3a in the part and the drain terminal of the transistor m3b are connected to the output terminal QB, and the gate terminals of the transistors m1b and m3b in the positive feedback part and the drain terminal of the transistor m3a are connected to the output terminal QB . In addition, between the drain terminal of the NMOS transistor m1a and the drain terminal of the PMOS transistor m3a, the NMOS transistor m2a which is synchronized with the clock signal CLK and used as a switch is connected, and between the drain terminal of the NMOS transistor m1b and the drain terminal of the...

Embodiment approach 3

[0116] Figure 5 It is a figure which shows an example of the structure of the dynamic comparator 500 of Embodiment 3. The comparator 500 includes: an input transistor section including NMOS transistors m11, m12, m21, m22, a positive feedback section (cross-coupled inverting latch section) including NMOS transistors m1a, m1b and PMOS transistors m3a, m3b, The gate terminals of the transistors m1a and m3a in the part and the drain terminal of the transistor m3b are connected to the output terminal QB, and the gate terminals of the transistors m1b and m3b in the positive feedback part and the drain terminal of the transistor m3a are connected to the output terminal QB . In addition, between the drain terminal of the NMOS transistor m1a and the drain terminal of the PMOS transistor m3a, the NMOS transistor m2a which is synchronized with the clock signal CLK and used as a switch is connected, and between the drain terminal of the NMOS transistor m1b and the drain terminal of the ...

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PUM

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Abstract

In a comparator for use in a parallel A / D converter, the comparator (100) is provided with reset transistors (mra, mrb). When the comparator (100) is in reset state, the PMOS transistors (mra, mrb) are provided with the inverted signal / CLK of a clock signal and the voltages at two internal nodes (Va, Vb) becoming a differential pair are reset forcibly to a predetermined reset voltage by the reset transistors (mra, mrb). The inverted signal / CLK of a clock signal is generated with a predetermined time lag. When the comparator (100) is in reset state, reset release timing of the internal nodes (Va, Vb) is delayed behind the comparison operation timing of the comparator. Consequently, even if the frequency of the clock signal and the frequency of an analog input signal are increased, voltage balance is improved at the internal nodes forming a differential pair when the comparator is in reset state, and voltage comparison precision is enhanced.

Description

technical field [0001] The present invention relates to a comparator that receives a plurality of differential voltage pairs and synchronizes with a clock signal to compare the differential voltages (voltage differences) of the plurality of differential voltage pairs, and a comparator that converts analog signals into digital signals An A / D converter, particularly an A / D converter having a parallel-type structure. Background technique [0002] In recent years, with the high speed of information communication, high speed and high capacity of optical disc pickup (Optic Disk Pick up), A / D converters with high speed and wide input frequency are required, and in order to reduce costs, it is necessary to save A / D converter with small area and low power consumption. [0003] Figure 14 The structure of the parallel A / D converter 1400 in the prior art is shown. High-speed analog / digital conversion is performed using this A / D converter. [0004] The A / D converter 1400 is composed ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K5/08H03M1/36
CPCH03M1/0607H03K5/2481H03M1/362H03M1/204
Inventor 中顺一须志原公治
Owner PANASONIC CORP
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