An irregular topology structure generation method for chip network

Abstract

An irregular topology generating method for a network-on-chip is disclosed, belonging the design field of the Internet-on-chip, characterized in that the method comprises the following steps of: dividing nodes in a communication diagram that describes the application of the network-on-chip into a plurality of sets; forming new nodes by using an edge router to connect all the nodes in each set, in order to form the new directional communication diagram; performing integrated division to the new directional communication diagram until a new set is unable to form or the number of the nodes is less than or equal to 5; then determining the number of core network routers and generating the core network according to the number of the nodes in the finally-formed communication diagram; simplifying the network by reducing the redundant edge routers. The invention has the characteristics of small area and low consumption in communication power on condition of meeting the communication demands of specific application.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, in particular to the field of on-chip interconnection network design. Background technique [0002] Integrated circuits have been advancing in accordance with Moore's Law. The number of IP (Intellectual Property) cores integrated in a single chip is increasing. The traditional bus-based on-chip interconnect structure has shown outstanding performance in terms of bandwidth, power consumption, reliability, and scalability. Increasingly, on-chip communication has replaced computation as the bottleneck in IC design. Network-on-Chip (NoC), as a key technology in the field of integrated circuit design, is used to solve the problem of on-chip interconnection caused by the increase in chip size. The network on chip is mainly composed of routers, network interfaces and physical links. [0003] Topology is a hot issue in the research of network-on-chip. The research in this area can be divided in...

AI Technical Summary

Problems solved by technology

At present, a problem that has not been well resolved in the research of irregular topology is the design automation problem, that is, how to generate the optimal or better irregular topology according to the specific directed communication graph.

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