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Methods and apparatus and system for issuing commands on a bus

A command and bus technology, applied in machine execution devices, concurrent command execution, instruments, etc., can solve the problems of consuming the effective area of ​​the chip and consuming the extra space of the first processor.

Inactive Publication Date: 2008-08-13
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, traditional systems require a large amount of logic to implement complex pointer manipulations, which consumes additional space on the first processor and consumes chip real estate

Method used

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  • Methods and apparatus and system for issuing commands on a bus
  • Methods and apparatus and system for issuing commands on a bus
  • Methods and apparatus and system for issuing commands on a bus

Examples

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Embodiment Construction

[0013] The present invention provides an improved method and apparatus for issuing commands onto a bus. Similar to conventional systems, the present invention can separate read and write commands into streams, store read commands in the read stream and write commands in the write stream. Additionally, the present methods and apparatus may use conventional read and write address conflict lists and dependency matrices to determine whether the command at the top of the read queue is dependent on a write command and / or whether the command at the top of the write queue is dependent on a read command. Furthermore, the present methods and apparatus may use blocking commands, such as "Ensured In-Order Execution of I / O" (EIEIO) or synchronous commands, to cause in-order execution of commands stored in one or more queues. EIEIO and sync commands are known to those skilled in the art and thus will not be described in detail here.

[0014] Unlike conventional systems, the present methods...

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PUM

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Abstract

The invention discloses a method, device and system for issuing commands to the bus. In a first aspect, a first method of issuing commands onto a bus of a system is provided. The first method includes the steps of: (1) receiving a first functional memory command in the system; (2) receiving a command that causes the system to execute the functional memory commands sequentially; (3) receiving a second functional memory command in the system command; and (4) using a dependency matrix to indicate that the second functional memory command needs to access the same address as the first functional memory command, regardless of whether the second functional memory command actually has an ordering to the first functional memory command dependency. The dependency matrix is ​​adapted to store data indicating whether a functional memory command received by the system has an ordering dependency on one or more functional memory commands previously received by the system. A number of other aspects are also provided.

Description

technical field [0001] The present invention relates generally to processors, and more particularly to methods and apparatus for issuing commands onto a bus. Background technique [0002] In conventional systems, a first processor may be coupled to a second processor through an input / output (I / O) interface. The first processor may receive commands from the second processor through the I / O interface to be placed on the bus. The first processor may separate the received commands into a stream of read commands and a stream of write commands, storing the read commands in a read queue and storing the write commands in a write queue. Conventional systems can maintain order between command streams by determining whether the read command at the top of the read queue is dependent on the completion of a pending write command and / or whether the write command at the top of the write queue is dependent on the completion of a pending read command. More specifically, conventional systems...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F13/1631
Inventor J·D·艾里什C·B·麦克布赖德
Owner INT BUSINESS MASCH CORP
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