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A method and apparatus for predicting branch instructions

一种分支指令、指令的技术，应用在程序控制设计、仪器、计算等方向，能够解决减小预测精度等问题

Inactive Publication Date: 2008-07-23
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, shrinking the branch history table in this way generally reduces prediction accuracy because the same predictor is used to predict branches over a wider range of instruction addresses

Method used

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  • A method and apparatus for predicting branch instructions
  • A method and apparatus for predicting branch instructions
  • A method and apparatus for predicting branch instructions

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Embodiment Construction

[0017] By way of non-limiting example, FIG. 1 illustrates a microprocessor 10, which may comprise a pipelined RISC microprocessor. In the illustrated embodiment, microprocessor 10 includes input / output (I / O) circuitry 12, instruction cache 14, data cache 16, and instruction pipeline 18, which includes front-end circuitry 20, execution units 22 and complete unit 24.

[0018] In operation, front-end circuitry 20 fetches instructions from instruction cache 14, which may be an on-board level 1 (L1) cache. Instructions are fetched according to a defined computer program flow that may include program branches or branches. Microprocessor 10 uses branch prediction to predict whether a conditional branch will or will not be taken so that it does not normally interrupt its instruction fetch operation when a conditional branch instruction is encountered.

[0019] The fetched instructions are decoded and issued to execution units 22, which may be implemented according to a superscalar a...

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PUM

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Abstract

A microprocessor comprising two branch history tables and configured to use a first of the branch history tables to predict a branch instruction as a hit in a branch target cache, and to use a first of the branch history tables The second of the two to predict the branch instruction as a miss in the branch target cache. Likewise, the first branch history table is configured to have an access speed that matches that of the branch target cache such that its prediction information is available in time with respect to a branch target cache hit detection, wherein The branch target cache hit detection may occur early in the microprocessor's instruction pipeline. The second branch history table thus only needs to be as fast as is needed to provide timely predictive information associated with recognizing a branch target cache miss as a branch instruction, for example at an instruction decode stage of the instruction pipeline.

Description

technical field [0001] The present invention relates generally to microprocessors, and in particular to branch predicting microprocessors. Background technique [0002] Pipelined microprocessors typically use branch prediction to avoid stalling their instruction pipelines while waiting to determine whether a conditional branch instruction should be taken. Branch prediction mechanisms allow such microprocessors to "guess" whether a conditional branch instruction will be taken or not taken before actually evaluating its branch condition. [0003] Common branch prediction methods rely on maintaining a branch history table containing many saturation counters or other trace indicators that provide branch prediction information. As an example, a two bit saturation counter counts up to a maximum value of 11 and down to a minimum value of 00, where a value of 11 represents a strong take, 10 represents a weak take, 01 represents a weak no take, and 00 represents a strong no take. S...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/42
CPCG06F9/3844
Inventor 托马斯·安德鲁·萨托里乌斯布赖恩·迈克尔·斯坦普尔杰弗里·托德·布里奇斯詹姆斯·诺里斯·迪芬德尔费尔罗德尼·韦恩·史密斯
Owner QUALCOMM INC
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