Clock switch method, clock switch unit, clock device and system

Abstract

The invention discloses a method embodiment for the clock switching, belonging to the technical field of the electronic communication, which comprises: judging whether the first clock signal output by the first clock module needs to be switched to the second clock signal output by the second clock module, if yes, the first clock signal with lower frequency is produced; the second clock signal and the first clock signal after the frequency decreasing are detected, and when the phases of the two clock signals are synchronous, the indicating information of the clock switching which switches the output clock signal of the first clock module to the output clock signal of the second clock module is output; according to the indicating information of the clock switching, the clock signal output by the first clock module is switched to the clock signal output by the second clock module. The invention also discloses a corresponding clock switching unit, a clock device and a system. The invention has an advantage of improving the harmful effects of the system performances caused by the clock switching.

Description

technical field [0001] The invention relates to the technical field of electronic communication, in particular to a method for realizing clock switching, a clock switching unit, a clock device and a system. Background technique [0002] In some electronic or communication systems, in order to improve the reliability of the clock module, more than one clock module is often configured in the system. Take the configuration of two clock modules as an example (referred to as the first clock module and the second clock module below). During system operation, both the first clock module and the second clock module are in the running state. If the first clock module When it is in the active state (the first clock module is correspondingly the active clock module), and provides clock signals to the service board, and the second clock module is in the standby state (the second clock module is correspondingly the standby clock module), if the first When the clock module fails, in orde...

AI Technical Summary

Problems solved by technology

[0007] In the above clock switching process, when the first clock module fails (or receives a status change indication), the first control unit and the second control unit will immediately change the output master status indication information, so that the selector from The first clock signal is switched to the second clock signal. However, if the switch occurs, both the first clock signal and the second clock signal are synchronized with the satellite clock signal. Because there is a delay between different clock modules and different clock modules The difference in the phase locking of the phase-locked loop makes the first clock signal and the second clock signal often have the same frequency but are not in phase. In this way, redundant clock pulses are likely to be generated during the clock switching process, or a large clock cycle occurs. changes (refer to Figure 2 and Figure 3), resulting in an automatic system reset or other adverse effects on system performance

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