Stacking wafer encapsulation structure with bus rack in lead rack

Abstract

The invention provides a stacked chip encapsulation structure with a collecting bracket arranged on a lead frame, which includes a lead frame consisting of a plurality of inner pin groups arranged relatively, a plurality of outer pin groups and a chip bearing seat, wherein, the chip bearing seat is arranged among a plurality of inner pin groups arranged relatively and forms height difference withthe inner pin groups; the stacked chip device is formed by a plurality of chip stacks and arranged on the chip bearing seat and is electrically connected with the inner pin groups; and an encapsulation body, used to wrap the stacked chip device and the lead frame, wherein, the lead frame includes at least one collecting bracket and is arranged among the inner pin groups and the chip bearing seat.

Description

technical field [0001] The invention relates to a multi-chip offset stacking packaging structure, in particular to a multi-chip offset stacking packaging structure in which a lead frame is provided with busbars. Background technique [0002] In recent years, three-dimensional (3D) packaging is being carried out in the back-end manufacturing process of semiconductors, in order to use the least area to achieve relatively large semiconductor integration (Integrated) or memory capacity. In order to achieve this goal, a method of using chip stacked (chip stacked) to achieve three-dimensional (Three Dimension; 3D) packaging has been developed at this stage. [0003] In the known technology, the chips are stacked by stacking a plurality of chips on a substrate, and then a wire bonding process is used to connect the plurality of chips to the substrate. FIG. 1A is a schematic cross-sectional view of a conventional stacked chip package structure with the same or similar chip size. A...

AI Technical Summary

Problems solved by technology

However, when the known technology stacks a plurality of chips of different sizes out of the stacked chip package structure 10 in the above-mentioned manner, since the size of the chip on the upper layer must be smaller, the stacked chip package structure 10 has a limit on the number of stacked chips.

[0007] Among the above two stacking methods, the method of using spacers 130 in FIG. 1A is likely to cause the disadvantage that the thickness of the stacked chip packaging structure 100 cannot be further reduced; and Figure 1B , since the chip size of the upper layer must be smaller, there will be a problem that the design or use of the chip will be limited

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