Data clock recovery circuit

Abstract

This invention relates to data clock restore circuit, which comprises impulse width edge test unit to receive positive and negative data, impulse extension unit, clock lock phase trace unit, clock filter unit, data relay unit and data sampling lock unit, wherein, the said positive and negative data orderly input impulse width edge test unit and to output impulse signal to the relative impulse extension unit; the said width extension unit outputs extension signal phase meter into clock lock phase to output filter clock.

Description

technical field [0001] The invention relates to a data clock recovery circuit, in particular to a data clock recovery circuit of an E1 / T1 low-speed data link in the communication field. Background technique [0002] In the existing communication field, data clock recovery is indispensable on many interfaces. The clock information is transmitted through the data, and the clock needs to be recovered from the data, and the data is also recovered at the same time. On various interfaces, when data is interfered by external signals, there is often a certain amount of jitter. Therefore, the data clock recovery circuit needs to be able to tolerate this jitter and recover data correctly. Therefore, the index of input jitter tolerance is also closely related to the data clock recovery circuit. The quality of the data clock recovery circuit determines the quality of the clock data. [0003] There are many kinds of current clock data recovery circuits, usually divided into high-speed ...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a kind of data clock recovery circuit, in order to overcome the PLL tracking slow defect in the prior art, solve the problem that the input jitter tolerance difference existing in the prior art is low; Using high-speed clock, designed for synchronous circuit, its reliability is high

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