Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Method for forming grid medium layer and estimating its electrical parameter

A gate dielectric layer and electrical parameter technology, which is applied in the manufacture of circuits, electrical components, semiconductors/solid-state devices, etc., can solve problems such as the inability to evaluate the electrical parameters of the gate dielectric layer online, and achieve improved electrical stability and Reliability, cost savings, and the effect of reducing R&D cycles

Inactive Publication Date: 2009-11-18
SEMICON MFG INT (SHANGHAI) CORP +1
View PDF7 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The invention provides a method for evaluating the gate dielectric layer to solve the existing problem that the electrical parameters of the gate dielectric layer cannot be evaluated online

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for forming grid medium layer and estimating its electrical parameter
  • Method for forming grid medium layer and estimating its electrical parameter
  • Method for forming grid medium layer and estimating its electrical parameter

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0021] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0022] The gate dielectric layer plays a very important role as an insulating layer between the gate and the conductive channel of the substrate. The physical characteristic parameters of the gate dielectric layer will affect the formed device leakage current, turn-on voltage, carrier migration performance, and response speed The isoelectric parameter is also referred to as the electrical parameter of the gate dielectric layer in the present invention. Especially with the development of semiconductor technology to the technical node of 90nm and below, the thickness of the gate dielectric layer has been reduced to 5nm or even smaller. Controlling process parameters to form a high-quality gate dielectric layer is a problem that process pe...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A method for evaluating the electrical parameters of the gate dielectric layer, comprising: measuring the film physical characteristic parameters of the gate dielectric layer and the electrical parameters of the device formed by the gate dielectric layer; fitting the physical characteristic parameters and electrical parameters The correlation curve between the electrical parameters and the calculation of the correlation coefficient; Find out the physical characteristic parameters that have a large correlation with the electrical parameters; Online measurement of the physical characteristic parameters of the gate dielectric layer; Through the physical characteristic parameters with a large correlation coefficient with the electrical parameters Estimate electrical parameters. The method of the invention can evaluate the electrical parameters of the grid dielectric layer on-line.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for evaluating electrical parameters of a gate dielectric layer and forming a gate dielectric layer. Background technique [0002] With the development of semiconductor technology, more devices need to be integrated in a limited area, and the size of corresponding devices needs to be reduced. With the help of advanced photolithography technology, such as 193nm, 157nm and immersion exposure technology, the gate length representing the semiconductor process level can reach 90nm, or even 65nm. The turn-on voltage applied to the gate gradually becomes smaller, and correspondingly, the thickness of the gate dielectric layer becomes thinner, so as to increase the response speed of the device. In particular, for the current semiconductor process of 90nm and below, the thickness of the gate oxide has been reduced to 5nm or even smaller. Chinese patent appli...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66H01L21/283H01L21/31H01L21/336
Inventor 刘云珍何永根郭佳衢
Owner SEMICON MFG INT (SHANGHAI) CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com