Apparatus and method for processing pretreated microinstruction asynchronous multilayer nest

A micro-instruction and pre-processing technology, which is applied in the direction of concurrent instruction execution, electrical digital data processing, program control design, etc., to achieve the effect of ensuring correct recovery

Inactive Publication Date: 2009-06-03
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] However, there is no technology to deal with abnormal multi-layer nesting of preprocessing micro-instructions at present. How to deal with abnormal multi-layer nesting of pre-processing micro-instructions is an important problem that needs to be solved urgently.

Method used

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  • Apparatus and method for processing pretreated microinstruction asynchronous multilayer nest
  • Apparatus and method for processing pretreated microinstruction asynchronous multilayer nest
  • Apparatus and method for processing pretreated microinstruction asynchronous multilayer nest

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Embodiment Construction

[0056] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0057] like figure 1 as shown, figure 1 It is a structural block diagram of a device for processing abnormal multi-layer nesting of preprocessing micro-instructions according to the present invention. The equipment provided by the present invention is a central processing unit (CPU) that handles the occurrence of abnormal multi-layer nesting of preprocessing microinstructions. Reorder Buffer (ROQ) 105 .

[0058] Wherein, the instruction fetching unit 101 includes an instruction register, an instruction cache, an instruction bypass buffer, a branch predictor, etc., and the specific composition structure can be adjusted correspondingly according to the complexity of the implemented system. The instruction fetching unit 1...

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Abstract

A method for processing abnormal multilayer-nesting of pretreated micro- command includes buffer-storing abnormal information by decoding element and decoding said information to generate address of micro- command, obtaining abnormal pretreated micro-command by decoding element as per said address and sending obtained micro-command to back-end component (BEC), clearing out command flow line of computer and buffer-storing reoccurred abnormal information (RAI) by decoding element as well as generating micro-command address of RAI if abnormal is occurred at BEC again or otherwise jumping BEC and executing abnormal processing program.

Description

technical field [0001] The invention relates to an internal abnormal processing technology of a complex instruction set computer, in particular to a device and a method for processing abnormal multi-layer nesting of preprocessing micro-instructions. Background technique [0002] A computer based on a complex instruction set (Complex Instruction Set Computer, CISC) refers to a computer with a complex instruction system based on microprograms. In a CISC system, a complex instruction generally needs to be translated into multiple microinstructions, and the translated multiple microinstructions are stored in the read-only memory (ROM) of the CPU, and the instruction pipeline in the processor processes these microinstructions , rather than complex instructions visible to the operating system prior to translation. [0003] Microinstructions can usually manipulate more register resources than complex instructions. For example, complex instruction sets can typically operate on 8 v...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/318G06F9/38
Inventor 段振中范东睿
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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