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Trap charge capturing quick flashing storage array structure and operating method thereof

A technology of a memory array and an operation method, applied in the field of operation of a flash memory array, can solve the problems of non-energy-side selective programming, inability to realize double-bit storage, etc., and achieve the effects of high integration, improved consistency, and increased capacity

Inactive Publication Date: 2009-01-14
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the use of a common source line structure, selective programming of the source cannot be performed, and double-bit storage of each unit cannot be realized.

Method used

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  • Trap charge capturing quick flashing storage array structure and operating method thereof
  • Trap charge capturing quick flashing storage array structure and operating method thereof
  • Trap charge capturing quick flashing storage array structure and operating method thereof

Examples

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Embodiment Construction

[0051] The present invention provides an operating method of a flash memory array that traps charge trapping. The specific embodiments of the present invention will be described below in conjunction with the drawings.

[0052] Figure 5 What is shown is a schematic diagram of the array structure of the SONOS flash memory proposed by the present invention. Among them, m SONOS flash memory cell strings are connected together to form a SONOS cell string STi. The number m of cells in each cell string is not limited to the 16 shown in the figure. A series of SONOS cell strings STi are respectively arranged in the row direction and the column direction to form a memory array. Each cell string also includes a bit line selection tube 501D and a source line selection tube 501S. In the row direction, the gate of each SONOS cell is commonly connected to a word line WLx (WL0 to WL15), and the gate of each bit line selection transistor in the row direction is commonly connected to a bit line ...

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PUM

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Abstract

The present invention relates to a trap charge captured type flash memory array structure and its operation method. Said invention adopts serial arrangement to arrange the serial memory array structure forming two-dimensional several repeated permutations on the substrate. Said structure includes a first selective transistor, several storage units and a second selective transistor, the transistors and storage units are serial-connected, the gate of storage unit is connected with word line, the gate of selective transistor is connected with selection line, and first end of said serial structure is connected with bit line, and its second end is connected with next adjacent bit line. Its operation method includes programming operation, erasion operation and fetch operation.

Description

Technical field [0001] The present invention belongs to non-volatile memory technology, and particularly relates to an array architecture in a SONOS (silicon-oxide-nitride-oxide-silicon) flash memory and a trap charge trap for programming, erasing and reading operations Type flash memory array operation method. Background technique [0002] Flash memory has the characteristics of storing data that will not be lost even after power failure, and is especially suitable for fields such as mobile communications and computer storage components. Some flash memories also have high-density storage capabilities and are suitable for applications such as large-capacity removable storage media. [0003] The traditional flash memory has a floating gate structure, which includes a tunnel oxide layer, a floating gate, a dielectric layer between the floating gate and the control gate, and a control gate. This kind of floating gate structure flash memory technology is more complicated; due to the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/115G11C16/02H01L27/11568
Inventor 潘立阳孙磊朱钧
Owner TSINGHUA UNIV
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