A semiconductor structure for electrostatic discharge protection

Abstract

A semiconductor structure for electrostatic discharge protection is presented. The semiconductor structure comprises a grounded gate nMOS (GGNMOS) having a substrate, a gate electrode, a source region and a drain region. A plurality of contact plugs is formed on the source and drain side. A plurality of first level vias is electrically coupled to the GGNMOS and has a substantially asymmetrical layout in the source and drain regions. A second level via(s) re-routes the ESD current to the desired first level vias. The uniformity of the current flow in the GGNMOS is improved.

Description

technical field [0001] The present invention relates to electrostatic discharge devices, and more particularly to obtaining uniformity of current flow in a grounded gate NMOS (GGNMOS). Background technique [0002] Electrostatic discharge (ESD) is a phenomenon in which electrostatic charges on non-conductive surfaces migrate through conductive materials. Since the electrostatic voltage is usually quite high, ESD can easily damage the substrate and other components of an integrated circuit. For example, when the relative humidity is high, an electrostatic voltage of hundreds to thousands of volts can be generated on a human body walking on a carpet, but when the relative humidity is low, an electrostatic voltage of more than 10,000 volts can be generated. Likewise, electrostatic voltages of hundreds to thousands of volts can be generated in a packaging machine or in a test circuit of an integrated circuit. Therefore, when a person or machine with static electricity touches ...

AI Technical Summary

Problems solved by technology

Note that even though all sub-transistors are turned on, the middle sub-transistor still conducts more current than the sub-transistors at both ends, so the middle transistor is more prone to damage

Images