Organizational scheduling method for multi-mode COS queue and apparatus thereof

A dispatching method and dispatching device technology, applied in the direction of instruments, electrical digital data processing, digital transmission systems, etc., can solve the problems of complex design, unfavorable cost control, high cost, etc., and achieve the effect of low cost

Active Publication Date: 2008-07-30
HISILICON TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This solution has the following disadvantages: not all flows need 4 queues, some flows may only need 1 queue or 2 queues, taking the user only needs 2 COS queues per flow as an example, using the above solution, Its queue resources, including the chip internal units at the head and tail of the queue, consume too much, which is not conducive to cost control
However, this method is complex in design, high in cost, and its data throughput is often limited

Method used

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  • Organizational scheduling method for multi-mode COS queue and apparatus thereof
  • Organizational scheduling method for multi-mode COS queue and apparatus thereof
  • Organizational scheduling method for multi-mode COS queue and apparatus thereof

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Embodiment Construction

[0031] see figure 1 , the device for organizing and scheduling multi-mode COS queues for user flows according to the present invention includes a first memory 10 , a second memory 20 , a first reading device 30 , a second reading device 40 and a computing device 50 .

[0032] Each address of the first memory 10 corresponds to a flow, and the content of each address indicates the number of COS queues of the corresponding flow.

[0033] Each bit of the second memory 20 corresponds to a COS queue, and each bit identifies whether the corresponding queue has a packet. It stores the flag corresponding to whether there is a packet in the COS queue.

[0034] Specifically, the first memory 10 and the second memory 20 may be random access memories.

[0035] Taking N=2 and the maximum number of streams being 2048 as an example, the meaning of the information stored in the two memories will be explained below.

[0036] see figure 2 , which is a schematic diagram of the storage struct...

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Abstract

This invention discloses a kind of organizing dispatching method for multimode COS queue aiming at user flow. It concludes: each address of the first memory is corresponded to one flow. The content indicates the number of COS queues containing in corresponded flow; each bit of the second memory is corresponded to one COS queue and identifies that whether the corresponding queue has packets; the number of COS queue to be dispatched is acquired from the first memory; the flag bits corresponded to COS queues, which are contained in the flow to be dispatched in the second memory, are determined. Whether the COS queues containing in the flow to be dispatched have packets is determined; COS queues which should be priority dispatched in the second memory is determined. This invention also discloses corresponding apparatus.

Description

technical field [0001] The invention relates to computer and network data communication technology, in particular to a method and device for organizing and scheduling multi-mode COS queues for user flows. Background technique [0002] In the data processing chip, there are generally two ways to organize the COS queue, one is the organization way of the COS queue based on the port, and the other is the way of organizing the COS queue based on the flow. [0003] The port-based COS queue organization method means that each egress port corresponds to a group of COS queues, and the data packets formed after the data streams are grouped enter the tails of different COS queues according to different service levels and priorities. At the opposite end of the group of COS queues, a specific priority scheduling algorithm is used to schedule packets out of the egress port in serial order. This method consumes less logical resources and is more economical, but the jitter of the exported...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/56G06F13/00
Inventor 徐兴利尚秋平
Owner HISILICON TECH
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