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Semiconductor device, method of manufacturing semiconductor device, and solid-state image sensor

a semiconductor and semiconductor technology, applied in semiconductor devices, electrical equipment, radio frequency controlled devices, etc., can solve the problems of increasing manufacturing costs, damage other parts, and deteriorating semiconductor integration density, so as to reduce the restriction on design necessary for avoiding charging damage, suppress transistor characteristics due to charging damage, and reduce design freedom

Pending Publication Date: 2022-08-18
SONY SEMICON SOLUTIONS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The technology described in this patent reduces the damage caused by charging in transistors, which means that less design restrictions are needed to avoid the damage and more flexibility is allowed for improving semiconductor integration.

Problems solved by technology

In recent years, improvements in semiconductor integration density have begun to deteriorate due to various factors such as limitations of microfabrication and increase in manufacturing cost.
At that time, there is a possibility that an electric charge of plasma colliding with a hole bottom during the excavation is charged inside the through hole and damage other parts via the wiring part to be connected.
Specifically, for example, there is a possibility that a thin insulating film (a gate insulating film or the like) in contact with any part electrically connected to the wiring part to be connected is destroyed or deteriorated.

Method used

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  • Semiconductor device, method of manufacturing semiconductor device, and solid-state image sensor
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  • Semiconductor device, method of manufacturing semiconductor device, and solid-state image sensor

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Experimental program
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Effect test

first embodiment

(A) First Embodiment

[0047]FIG. 1 is a view illustrating a cross section of a main part of a semiconductor device 100 according to the present embodiment.

[0048]The semiconductor device 100 is a semiconductor chip formed using silicon or the like and includes a vertical electrode 30 extending along a thickness direction of the semiconductor device 100. Hereinafter, a portion in the semiconductor chip, the portion serving as a base before the vertical electrode 30 is formed, is called base 10.

[0049]The vertical electrode 30 electrically connects wiring 11 extending along one surface 10A of the base 10 and a portion to be connected T such as an electrode pad inside the base 10. The vertical electrode 30 is a concept including various aspects and includes a bottomed via and a contact formed in a bottomed hole extending along a thickness direction of the base 10.

[0050]Note that, hereinafter, a case in which specific wiring in a wiring layer 10b stacked and formed on a surface of a semicon...

second embodiment

(B) Second Embodiment

[0079]FIG. 8 is a view illustrating a cross section of a main part of a semiconductor device 200 according to the present embodiment. The semiconductor device 200 has a similar configuration to the above-described semiconductor device 100 except shapes of a low-resistance film and an insulating film in a vicinity of a hole bottom and a barrier metal film and a conductive portion formed on the low-resistance film and the insulating film.

[0080]Therefore, hereinafter, shapes and a method of manufacturing the low-resistance film and the insulating film in the vicinity of the hole bottom and the barrier metal film and the conductive portion formed on the low-resistance film and the insulating film of the semiconductor device 200 will be mainly described and detailed description of other configurations is omitted, and signs are given by adding 2 to the beginning of the signs of the configuration of the semiconductor device 100 as necessary.

[0081]A low-resistance film ...

third embodiment

(C) Third embodiment

[0091]FIG. 12 is a view illustrating a cross section of a main part of a semiconductor device 300 according to the present embodiment. The semiconductor device 300 has a similar configuration to the above-described semiconductor device 100 except the number of times of stacking of a low-resistance film.

[0092]Therefore, hereinafter, a shape and a manufacturing method regarding stacking of the low-resistance film of the semiconductor device 300 will be mainly described and detailed description of other configurations is omitted, and signs are given by adding 3 to the beginning of the signs of the configuration of the semiconductor device 100 as necessary.

[0093]A low-resistance film 314 of the semiconductor device 300 is similar to the low-resistance film 14 of the semiconductor device 100 in being continuously provided from a vicinity of an opening portion 312a to a vicinity of a hole bottom 312b of a vertical hole 312 inside an insulating film 313.

[0094]The low-re...

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Abstract

To suppress variation in transistor characteristics due to charging damage to relieve restrictions on design necessary for avoiding the charging damage and improve the degree of freedom in design for increasing semiconductor integration. A semiconductor device includes a vertical electrode formed in a vertical hole extending from an opening portion toward a portion to be connected in a thickness direction of a base, and having a structure in which a barrier metal film and a conductive material are stacked sequentially from a side close to an insulating film exposed to the vertical hole, and a low-resistance film provided to lie between the barrier metal film and the insulating film except a vicinity of the portion to be connected, and having a lower resistance value than a resistance value of the insulating film.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application is a divisional application of U.S. patent application Ser. No. 16 / 349,886, filed on May 14, 2019, is a U.S. National Phase of International Patent Application No. PCT / JP2017 / 040764 filed on Nov. 13, 2017, which claims priority benefit of Japanese Patent Application No. JP 2016-250522 filed in the Japan Patent Office on Dec. 26, 2016. Each of the above-referenced applications is hereby incorporated herein by reference in its entirety.TECHNICAL FIELD[0002]The present technology relates to a semiconductor device, a method of manufacturing a semiconductor device, and a solid-state image sensor.BACKGROUND ART[0003]In recent years, improvements in semiconductor integration density have begun to deteriorate due to various factors such as limitations of microfabrication and increase in manufacturing cost. Three-dimensional mounting technologies have drawn attention as technologies that overcome this situation. The three-dimensio...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L27/146H01L21/3065
CPCH01L27/14636H01L27/1469H01L27/14634H01L21/3065H01L21/8234H01L27/088H01L21/76898
Inventor SHIGETOSHI, TAKUSHI
Owner SONY SEMICON SOLUTIONS CORP
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