Hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities

Abstract

Method, apparatus and computer program product for hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities comprising extracting design heterogeneity extremities from an RTL design; accounting for the design heterogeneity extremities during macro clock and data signals activity abstraction to generate improved macro activity abstractions; accounting for the design heterogeneity extremities during macro clock and data switching capacitance abstraction to generate improved macro capacitance abstractions; and using improved macro activity abstractions and improved macro capacitance abstractions during hierarchical chip power analysis.

Description

BACKGROUNDField of the Invention[0001]The field of the present disclosure is chip power analysis, or, more specifically, methods, apparatus, and products for hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities.Description of Related Art[0002]Modern fin field-effect transistor (FinFET-based) microprocessors' dynamic power consumes a lot of chip power under high utilization conditions. Power consumption is important in design because it affects cost and reliability. Microprocessors cater to a broad range of workloads, and each workload has a unique power signature. In addition to heterogeneity across workloads, there is notable heterogeneity in power profile across the chip, even within IP blocks. Microprocessor designs are power aware in order to control power consumption.[0003]One of the difficulties in designing modern microprocessors is swift, accurate power modeling. Particularly as devices...

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Benefits of technology

[0004]Methods, systems, and apparatus for hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities are disclosed in this specification. Methods, systems, and apparatus for hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities include extracting design heterogeneity extremities from an RTL design; accounting for the design heterogeneity extremities during macro clock and data signals activity abstraction to generate improved macro activity abstractions; accounting for the design heterogeneity extremities during macro clock and data switching capacitance abstraction to generate improved macro capacitance abstractions; and using improved macro activity abstractions and improved macro capacitance abstractions during hierarchical chip power analysis.

Problems solved by technology

Modern fin field-effect transistor (FinFET-based) microprocessors' dynamic power consumes a lot of chip power under high utilization conditions.

Power consumption is important in design because it affects cost and reliability.

In addition to heterogeneity across workloads, there is notable heterogeneity in power profile across the chip, even within IP blocks.

One of the difficulties in designing modern microprocessors is swift, accurate power modeling.

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