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Apparatus and method for a compressed stack representation for hierarchical acceleration structures of arbitrary widths

a stack representation and hierarchical acceleration technology, applied in image memory management, instruments, computing, etc., can solve the problems of not having all rendered pixels accessible for computing a denoised portion of the image, and being too resource-intensive for real-time performan

Active Publication Date: 2020-07-02
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The invention relates to a method and system for performing more efficient ray tracing operations in graphics processing. More specifically, the invention addresses the issue of denoising in real-time ray tracing with smooth, noisless images. The invention proposes a method for performing distributed denoising operations across multiple nodes and a machine learning method for continuously training and updating a denoising engine during runtime. The technical effects of the invention include improved performance and quality of real-time ray tracing, as well as more efficient and effective denoising for smooth, noisless images.

Problems solved by technology

Widely used in cinematic rendering, it was considered too resource-intensive for real-time performance until just a few years ago.
If rendering is being done across multiple devices, they may not have all rendered pixels accessible for computing a denoised portion of the image.

Method used

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  • Apparatus and method for a compressed stack representation for hierarchical acceleration structures of arbitrary widths
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  • Apparatus and method for a compressed stack representation for hierarchical acceleration structures of arbitrary widths

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Network Implementations

[0220]There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network may be implemented as an acyclic graph in which the nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer that are separated by at least one hidden layer. The hidden layer transforms input received by the input layer into a representation that is useful for generating output in the output layer. The network nodes are fully connected via edges to the nodes in adjacent layers, but there are no edges between nodes within each layer. Data received at the nodes of an input layer of a feedforward network are propagated (i.e., “fed forward”) to the nodes of the output layer via an activation function that calculates the states of the nodes of each successive layer in the network based on coefficients (“weights”) respectively associated with each of the edges connecting the layers. ...

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Abstract

Apparatus and method for a compressed stack representation for a BVH. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; traversal / intersection circuitry to traverse one or more of the rays through the hierarchically arranged nodes of the BVH and intersect the one or more rays with primitives contained within the nodes; a short traversal stack of a fixed size comprising a specified number of entries fewer than the number of child nodes beneath the parent node, each entry associated with a child node at the current BVH level, the entries ordered from top to bottom within the short traversal stack based on a sorted distance of each respective child node, wherein each entry includes a field to indicate whether that entry is associated with a final child in the current BVH level; wherein the traversal / intersection circuitry is to process entries from the top of the traversal stack, removing entries as they are processed, the traversal / intersection circuitry to determine that a current entry is associated with the final child node at the current BVH level by reading a first value in the field.

Description

BACKGROUNDField of the Invention[0001]This invention relates generally to the field of graphics processors. More particularly, the invention relates to an apparatus and method for performing more efficient ray tracing operations.Description of the Related Art[0002]Ray tracing is a technique in which a light transport is simulated through physically-based rendering. Widely used in cinematic rendering, it was considered too resource-intensive for real-time performance until just a few years ago. One of the key operations in ray tracing is processing a visibility query for ray-scene intersections known as “ray traversal” which computes ray-scene intersections by traversing and intersecting nodes in a bounding volume hierarchy (BVH).[0003]Denoising has become a critical feature for real-time ray tracing with smooth, noiseless images. Rendering can be done across a distributed system on multiple devices, but so far the existing denoising frameworks all operate on a single instance on a s...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06T1/60G06T15/06G06T17/00
CPCG06T2210/08G06T15/06G06T1/60G06T17/005G06T2210/21G06T15/005G06T15/30
Inventor VAIDYANATHAN, KARTHIKWOOP, SVENBENTHIN, CARSTEN
Owner INTEL CORP
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