Split Gate Nanocrystal Memory Integration

Abstract

A process integration is disclosed for fabricating non-volatile memory (NVM) cells having spacer control gates (108) along with a high-k-metal-poly select gate (121, 123, 127) and one or more additional in-laid high-k metal CMOS transistor gates (121, 124, 128) using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention is directed in general to integrated circuit devices and methods for manufacturing same. In one aspect, the present invention relates to the fabrication of CMOS metal gate devices and non-volatile memory devices integrated on a single substrate or chip.[0003]2. Description of the Related Art[0004]Non-volatile memory devices, such as EEPROM and flash memory, are used in computers and other electronic devices to store data and / or programming instructions that can be electrically erased and reprogrammed and that must be saved when power is removed. Embedded non-volatile memory (NVM) has become increasingly important in applications ranging from data and code storage to circuit trimming and customization. By embedding a non-volatile memory in a CMOS device, a single chip device can be manufactured and configured for a variety of applications. While the introduction of novel gate stack materials for for...

AI Technical Summary

Benefits of technology

The present invention relates to the fabrication of integrated circuit devices and methods for manufacturing same. More specifically, the invention is about the integration of CMOS metal gate devices and non-volatile memory devices on a single chip. The invention addresses the challenges of integrating non-volatile memory cells with CMOS transistors using a gate-last process. The invention provides a solution for fabricating a shared gate-last process sequence that replaces sacrificial poly select gates and poly transistor gates with high-k metal gates having enhanced isolation between the high-k metal select gate and spacer control gate. The invention also includes a process for forming split-gate nanocrystal thin film storage non-volatile memory bitcells with spacer control gates and in-laid high-k metal select gates. The invention provides a compact and efficient solution for integrating non-volatile memory cells with CMOS transistors on a single chip.

Problems solved by technology

While the introduction of novel gate stack materials for forming high-k metal gate stacks using gate last processes has improved device performance and reduced feature sizes for transistor devices, there are a number of integration options and challenges associated with the integration of such novel materials with existing polysilicon nanocrystal thin film storage bitcells.

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