System and method for CMP having multi-pressure zone loading for improved edge and annular zone material removal control

Abstract

In one aspect, the invention provides a method for planarizing a circular disc-type semiconductor wafer or other substrate. The method includes the steps of pressing a retaining ring surrounding the wafer against a polishing pad at a first pressure; pressing a first peripheral edge portion of the wafer against the polishing pad with a second pressure; and pressing a second portion of the wafer interior to the peripheral edge portion against the polishing pad with a third pressure. The second pressure may be provided through a mechanical member in contact with the peripheral edge portion; and the second pressure may be a pneumatic pressure against a backside surface of the wafer. Desirably, the pneumatic pressure is exerted through a resilient membrane, or is exerted by gas pressing directly against at least a portion of the wafer backside surface. A carrier or subcarrier for a CMP apparatus that includes: a plate having an outer surface; a first pressure chamber for exerting a force to urge the plate in a predetermined direction; a spacer coupled to a peripheral outer edge of the plate; a membrane coupled to the plate via the spacer and separated from the plate by a thickness of the spacer; and a second pressure chamber defined between the membrane and the plate surface for exerting a second force to urge the membrane in a third predetermined direction. Substrate, such as a semiconductor wafer, processed or fabricated according to the invention.

Description

RELATED APPLICATIONS [0001] This application is a divisional of U.S. patent application Ser. No. 10 / 401,272 filed Mar. 27, 2003, which is a continuation of U.S. patent application Ser. No. 09 / 570,369 filed May 12, 2000, now U.S. Pat. No. 6,558,232.FIELD OF INVENTION [0002] This invention pertains generally to systems, devices, and methods for polishing and planarizing semiconductor wafers, and more particularly to systems, devices, and methods utilizing multiple planarization pressure zones to achieving high-planarization uniformity across the surface of a semiconductor wafer. BACKGROUND OF THE INVENTION [0003] As feature size decreases, density increases, and the size of the semiconductor wafer increase, Chemical Mechanical Planarization (CMP) process requirements become more stringent. Wafer to wafer process uniformity as well as intra-wafer planarization uniformity are important issues from the standpoint of producing semiconductor products at a low cost. As the size of dies incr...

AI Technical Summary

Problems solved by technology

Wafer to wafer process uniformity as well as intra-wafer planarization uniformity are important issues from the standpoint of producing semiconductor products at a low cost.

As the size of dies increases a flaw in one small area increasing results in rejection of a relatively large circuit so that even small flaws have relatively large economic consequences in the semiconductor industry.

Efforts to simultaneously solve these problems have not heretofore been completely successful.

These inserts are problematic because they frequently result in process variation leading to substrate-to-substrate variation.

This tends to make the initial period of use more like the later period of use, however, unacceptable processes variations are still observed.

Such fabrication increases the costs of the head and of the machine, particularly if multiple heads are provided.

As the size of structures (feature size) on the semiconductor wafer surface have been reduced to smaller and smaller sizes, now typically about 0.2 microns, the problems associated with non-uniform planarization have increased.

When so called hard backed planarization heads, that is heads that press the backside of the semiconductor wafer with a hard surface, the front surface of the wafer may not conform to the surface of the polishing pad and planarization non-uniformities may typically result.

When such wafer surface distortion occurs, the high spots are polished at the same time as the low spots give some degree of global uniformity but actually producing a bad planarization result.

That is too much material from traces in some areas of the wafer will be removed and too little material from others.

When the amount of material removed is excessive, those die or chips will not be useable.

While some attempts have been made to utilize soft backed CMP heads, they have not been entirely satisfactory.

Unfortunately, while such approaches may provides a soft backed head it does not permit independent adjustment of the pressure at the edge of the wafer and at more central regions to solve the wafer edge non-uniformity problems.

However, even these attempts were not entirely satisfactory as the planarization pressure at the outer peripheral edge of the wafer was only indirectly adjustable based on the retaining ring pressure.

It was not possible to extend the effective distance of a retaining ring compensation effect an arbitrary distance into the wafer edge.

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