NAND flash memory with densely packed memory gates and fabrication process

a technology of memory gates and nand flash memory, which is applied in the direction of solid-state devices, semiconductor devices, instruments, etc., can solve the problems of difficult to form a high-voltage coupling ratio which is sufficient for program and erase operations, and is used in very high-density data storage applications

Inactive Publication Date: 2006-01-26
SILICON STORAGE TECHNOLOGY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0011] It is in general an object of the invention to provide a new a

Problems solved by technology

Its relatively large cell size prevents it from being used in very high density data storage applications.
However, as the fabrication process advances to very smaller geome

Method used

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  • NAND flash memory with densely packed memory gates and fabrication process
  • NAND flash memory with densely packed memory gates and fabrication process
  • NAND flash memory with densely packed memory gates and fabrication process

Examples

Experimental program
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Embodiment Construction

[0022] As illustrated in FIG. 2, the memory includes an array of NAND flash memory cells 36 which are arranged in rows between bit line diffusions 37 and a common source diffusion 38 formed in a P-type well 39 in the upper portion of a substrate 41 and doped with an N-type material. As discussed more fully hereinafter, in the preferred process of fabricating the cell array, the cells are formed in two groups 36a, 36b, with the cells in one group being interposed between the cells in the other. However, it will be understood that the array can be fabricated by other processes and that all of the cells can be formed in a single group.

[0023] The cells have memory or control gates 42a, 42b and charge storage gates 43a, 43b, with the control gates positioned above and aligned with the charge storage gates. A row select gate 46 is formed at the end of the row next to the bit line diffusion, with a passive (unused) charge storage gate 43a beneath it. The select gate partially overlaps the...

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Abstract

NAND flash memory cell array and fabrication process in which cells having memory gates and charge storage layers are densely packed, with the memory gates in adjacent cells either overlapping or self-aligned with each other. The memory cells are arranged in rows between bit line diffusions and a common source diffusion, with the charge storage layers positioned beneath the memory gates in the cells. The memory gates are either polysilicon or polycide, and the charge storage gates are either a nitride or the combination of nitride and oxide. Programming is done either by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates or by hot hole injection from the silicon substrate to the charge storage gates to build up a positive charge in the charge storage gates. Erasure is done by channel tunneling from the charge storage gates to the silicon substrate or vice versa, depending on the programming method. The array is biased so that all of the memory cells can be erased simultaneously, while programming is bit selectable.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of Invention [0002] This invention pertains generally to semiconductor memory devices and, more particularly, to a NAND flash memory and process of fabricating the same. [0003] 2. Related Art [0004] Nonvolatile memory is currently available in several forms, including electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash EEPROM. Flash memory has been widely used for high volume data storage in devices such as memory cards, personal digital assistants (PDA's), cellular phones, and MP3 players. Such applications require high density memory, with smaller cell size and reduced cost of manufacture. [0005] The traditional NOR-type stack-gate flash memory cell usually has a bit line contact, a source region, a floating gate, and a control gate, with the control gate being positioned directly above the floating gate. Its relatively large cell size prevents it from being used in ...

Claims

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Application Information

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IPC IPC(8): H01L29/94H01L27/108H01L29/76H01L31/119
CPCG11C16/0483H01L27/11524H01L27/11521H01L27/115H10B69/00H10B41/30H10B41/35
Inventor TUNTASOOD, PRATEEPFAN, DER-TSYRCHEN, CHIOU-FENG
Owner SILICON STORAGE TECHNOLOGY
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