Staggered memory cell array

Abstract

A method of placing a cell in an array is disclosed. The method includes placing the cell a plurality of times (600, 602, 604) in a first array. The cell is also placed a plurality of times (606, 608, 610) in a second array. The second array is placed adjacent and offset from the first array by an offset distance (O2).

Description

technical field [0001] The present invention relates generally to electronic circuits, and more particularly to geometry efficiency of semiconductor integrated circuits. Background technique [0002] The growing popularity of portable electronic devices poses enormous challenges to manufacturers. The ever-increasing capabilities of electronic devices are constrained by considerations such as cost, size, weight, and battery life. These considerations have led to higher and higher integration levels of semiconductors. Therefore, portable electronic devices often embed memory, control functions, signal processors, and other circuit functions on a single integrated circuit. Further optimization of these portable electronic devices requires even further reductions in geometry size and the space between these geometries. However, reducing the geometric size and space of semiconductor integrated circuits is limited by state-of-the-art manufacturing equipment. Reducing geometry ...

AI Technical Summary

Problems solved by technology

Therefore, the size of a single memory cell and the corresponding array size is limited by these critical dimensions

Images