Semiconductor device having a structure to improve contact processing margin, and method of fabricating the same

Abstract

The present invention relates to a semiconductor device having a structure to improve contact processing margin, and method of fabricating the same. The method for fabricating a semiconductor device includes: (a) selectively etching the first insulating layer and conductive layer of the semiconductor substrate to form a first insulating pattern, a first conductive pattern, and a second conductive pattern; (b) forming a spacer on sidewalls of the first insulating pattern, the first conductive pattern, and the second conductive pattern; (c) depositing the second insulating layer on the surface of the substrate which includes the pattern, dry etching the second insulating layer with the photoresist pattern to form the second insulating pattern; (d) removing the photoresist pattern and forming the first and the second self-aligned metal silicides on the exposed substrate and the second conductive pattern; (e) depositing the third insulating layer on the surface of the substrate which includes the pattern, selectively etching the third insulating layer to form the first and second contactors connecting the first and the second self-aligned metal silicides layers, forming the second insulating layer of the step (c) to entirely expose the upper surface of the second conductive pattern, forming the second self-aligned metal silicides of the step (d) to entirely cover the upper surface of the second conductive pattern.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2005-0074210 filed on Aug. 12, 2005, the entire contents of which are incorporated herein by reference. technical field [0002] The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a structure with improved contact processing margin and a method of manufacturing the same. Background technique [0003] Short spacing between contacts and non-salicide regions often results in insufficient processing margins when fabricating semiconductor devices including SRAMs. Misalignment due to insufficient processing margins in the contact formation step can lead to overetching of the underlying conductive layer. Excessive etching of the conductive layer adversely affects leakage current characteristics, degrading reliability and yield of semiconductor devices. [0004] figure 1 A partial design diagram of a conve...

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Problems solved by technology

Excessive etching of the conductive layer adversely affects leakage current characteristics, degrading reliability and yield of semiconductor devices

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