Method and apparatus for realizing clock active/standby changeover error-free

Abstract

The invention discloses a method for achieving the clock main equipment reversing without code error, which comprises the following steps: it links the hardware of the two clock units so that the clock signal can transmit to each other; the main clock unit controls the output clock signal by locking phase algorithm so that the output clock signal keeps the uniform with the input external guideline clock signal, and the stand-by clock unit real-time follow-ups and locks the output clock signal of the main clock unit; when it has the main equipment reversing, the stand-by clock unit controls the output clock signal by the control value of the main clock unit so that the output signal after reversing has the same frequency and the same phase with the clock signal before the reversing. It also discloses an appliance for achieving the clock main equipment reversing without code error.

Description

technical field [0001] The invention relates to a clock synchronization technology in the communication field, in particular to a method and a device for avoiding code errors generated by a service single board when the master and backup clocks are switched. Background technique [0002] In a synchronous digital communication network, the synchronization between network element nodes in the network is realized by a clock unit. The currently widely used clock synchronization method is the master-slave synchronization method. The master-slave synchronization method adopts a series of hierarchical clocks, and each level of clock tracks the upper level clock and maintains synchronization with the upper level clock. In the network, generally there is a network head connected to the reference clock. The reference clock is a clock with relatively high precision, and the rest of the network elements are synchronized with the reference clock. The master-slave synchronization method ...

AI Technical Summary

Problems solved by technology

Although the two clock units track the same clock source, due to the differences in hardware devices and the differences in software algorithm operation and processing, the clock frequencies output by the two clock units are the same, but the phases are different. This phenomenon is called the same frequency out of phase

[0005] Therefore, when the active / standby switchover occurs between the two clock units, the business will be damaged

Since the output clocks of the two clock units have the same frequency and different phases, the clocks cannot transition smoothly during active / standby switchover, resulting in bit errors on the service boards, resulting in momentary interruption or interruption of services

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