Output stage structure

Abstract

The invention relates to an output stage structure, which includes first and second p-type MOS transistors and first and second n-type MOS transistors, wherein the MOS transistors are made by double-well technology. The source of the first p-type MOS transistor is connected to the voltage source, and the gate is connected to the first voltage; the source of the second p-type MOS transistor is connected to the drain of the first p-type MOS transistor, the gate is connected to the second voltage, and the drain is connected to the second voltage. output pad; the drain of the first n-type MOS transistor is connected to the output pad, and the gate is connected to the third voltage; the drain of the second n-type MOS transistor is connected to the source of the first n-type MOS transistor, and the gate is connected to the fourth voltage, The source is connected to a ground point. The third and fourth substrate terminals are coupled to different fifth and sixth reference voltages. The first and second p-type MOS transistors and the first and second n-type MOS transistors form a double well structure. The double well structure has deep n-type well regions and multiple independent n-type well regions on the p-type substrate, and multiple independent p-type well regions on the deep n-type well region.

Description

technical field [0001] The invention provides an output stage structure, especially an output stage structure of an ultra-high withstand voltage complementary metal oxide semiconductor transistor. Background technique [0002] With the evolution of process technology, the circuits of metal oxide semiconductor (MOS) transistors are also designed in the direction of reducing size, increasing speed, reducing power consumption and lowering voltage. As the process evolves, the core circuit will use a lower voltage source to increase the performance of the circuit. For example, when the core circuit is produced with 0.5 μm process technology, the voltage source VDD used is 5.0V, but when the core circuit is produced with 0.25 μm process technology, the voltage source VDD used is 2.5V. However, the interface or peripheral circuits often do not reduce the power supply along with the progress of the core circuit due to historical or specification reasons. For example, the TTL (Tran...

AI Technical Summary

Problems solved by technology

[0006] figure 2 Since all PMOSs share the same n-type well 302 and all NMOSs share the same p-type substrate 304, it is impossible to control the bias voltage independently for the substrate terminal of a single NMOS or PMOS.

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