Output stage structure

Abstract

The invention provides a stage structure of output, which consists of a first p-type metal oxide semiconductor (MOS) transistor, a second p-type MOS transistor, a first n-type MOS transistor and a second n-type MOS transistor. The MOS transistors are prepared by applying the twin-well process. The source electrode (SE) of the first p-type MOS transistor is connected with a voltage source, and the grid electrode of the first p-type MOS transistor is connected with a first voltage. The SE of the second p-type MOS transistor is connected with the drain electrode of the first p-type MOS transistor, while the grid electrode of the second p-type MOS transistor is connected with a second voltage. The drain electrode of the second p-type MOS transistor is connected with an output pad. The drain electrode of the first n-type MOS transistor is connected with the output pad, and the grid electrode of the first n-type MOS transistor is connected with a third voltage. The drain electrode of the second n-type MOS transistor is connected with the source electrode of the first n-type MOS transistor, and the grid electrode of the second n-type MOS transistor is connected with a fourth voltage. The source electrode of the second n-type MOS transistor is connected with a touch-down point. The endpoints of third and fourth matrixes are coupled to different fifth and sixth reference voltages. The first and second p-type MOS transistors and the first and second n-type MOS transistors together form a twin-well structure, wherein a deep n-type well region and a plurality of independent n-type well regions are formed on a p-type substrate. The deep n-type well region is provided with a plurality of independent p-type well regions.

Description

technical field [0001] The invention provides an output stage structure, especially an output stage structure of an ultra-high withstand voltage complementary metal oxide semiconductor transistor. Background technique [0002] With the evolution of process technology, the circuits of metal oxide semiconductor (MOS) transistors are also designed in the direction of reducing size, increasing speed, reducing power consumption and lowering voltage. As the process evolves, the core circuit will use a lower voltage source to increase the performance of the circuit. For example, when the core circuit is produced with 0.5 μm process technology, the voltage source VDD used is 5.0V, but when the core circuit is produced with 0.25 μm process technology, the voltage source VDD used is 2.5V. However, the interface or peripheral circuits often do not reduce the power supply along with the progress of the core circuit due to historical or specification reasons. For example, the TTL (Tran...

AI Technical Summary

Problems solved by technology

[0006] figure 2 Since all PMOSs share the same n-type well 302 and all NMOSs share the same p-type substrate 304, it is impossible to control the bias voltage independently for a single NMOS or PMOS substrate terminal.

Images