Binary adder circuit and method for producing carry logical circuit used by it

Abstract

A binary adder circuit including a carry logic circuit and selection logic. The carry logic circuit uses group generate and propagate signals to produce complementary carry signals. The selection logic produces one of two presums dependent on the complementary carry signals. In a method for producing a carry logic circuit, a group generate logic function GI, I+1=GI OR GI+1 AND PI is to be performed. When GI+1=CI+1, GI, I+1=CI, arrival times of generate signals GI and GI+1, are investigated. If GI arrives before GI+1, a complex AND-OR-INVERT gate is used, otherwise a cascaded pair of NAND gates is selected. To produce a complementary carry signal, a logic function GI, I+1'=GI' AND GI+1' OR PI' is to be performed. If the generate signal GI' arrives before GI+1', a complex OR-AND-INVERT gate is used, otherwise a cascaded pair of NOR gates is selected.

Description

technical field [0001] This invention relates generally to binary adder circuits, and more particularly to fast binary adder circuits for use in digital processors. Background technique [0002] Modern processors (such as microprocessors) often include some binary adder circuits (ie, "adders"). For example, an adder is commonly used in an integer arithmetic logic unit (ALU) that performs addition, subtraction, multiplication, and division. A floating point processor may include two adders: one for the mantissa and one for the exponent. Additional adders can be used to calculate relative addresses for memory access and branch instructions. [0003] In many processor designs, the time required to perform addition operations in the ALU limits the speed of the processor. In general, binary adders are performance-hungry components of modern processors. Also, as the frequency of the processor clock signal increases and its period decreases, it becomes extremely difficult to im...

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Problems solved by technology

Also, as the frequency of the processor clock signal increases and its period decreases, it becomes extremely difficult to implement a "wide" adder (such as a 64-bit adder) that generates the sum and carry signals during a single cycle of the processor clock signal

[0004] Although adders implemented in dynamic logic can calculate the sum and carry signals faster than static logic implementations, static logic devices are still satisfactory due to the generally higher power consumption of dynamic logic circuits and increased sensitivity to noise

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