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Partial response maximum likelihood system possessing branch estimating equipment

A partial response, estimator technology, used in analog-to-digital converters, data representation error detection/correction, digital signal error detection/correction, etc., to solve problems such as circuit requirements and inefficiency

Inactive Publication Date: 2004-03-31
MEDIATEK INC
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the adaptive channel estimator is not only inefficient, but also requires many redundant circuits

Method used

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  • Partial response maximum likelihood system possessing branch estimating equipment
  • Partial response maximum likelihood system possessing branch estimating equipment
  • Partial response maximum likelihood system possessing branch estimating equipment

Examples

Experimental program
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Embodiment Construction

[0026] First, the reference signs in the present invention are explained: 60, 70, 80--PRML system, 62--analog-to-digital converter, 63--Viterbi decoder, 64, 74--branch estimator, 641-- Demultiplexer, 642--characteristic value calculation unit, 81, 87, 89--digital-analog converter, 82--digital cutter, 83--sequence control unit, 84--multiplexer, 85--multiple Phase-locked loop, 86--gain control unit, 88--offset value control unit, 90--analog gain controller.

[0027] The PRML system with branch estimator of the present invention will be described in detail below with reference to the drawings.

[0028] Figure 6 A block diagram of a first embodiment of the PRML system with branch estimator of the present invention is shown. As shown in the figure, the PRML system 60 includes: an analog-to-digital converter 62 , a Viterbi decoder 63 , and a branch estimator 64 .

[0029] The branch estimator 64 used in the PRML system of the present invention is different from a general channel...

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Abstract

The invention provides a part response maximum likelihood (PRML) system having a branch estimating device which comprises, an analog-to-digital converter for receiving an analog input signal, and transforming the analog input signal into digital signal sequence according to the triggering of the sampling clock, a branch estimating device for receiving the digital signal sequence and estimating each of the branch characteristic value, and a Viterbi code converter for receiving the digital signal sequence and the branch characteristic value and decoding the output signal. The PRML system by theinvention can reduce the circuit and raise the speed.

Description

technical field [0001] The present invention relates to a Partial Response Maximum Likelihood (PRML) system, in particular to a PRML system composed of a branch estimator and an adjustable (VITERBI) decoder. Background technique [0002] The Partial Response Maximum Likelihood (PRML) system can reliably read (retrieve) 8 to 14-bit modulation (Eight -to-Fourteen Modulation, EFM) signal. Also, a Viterbi decoder is often used in the PRML system to achieve maximum likelihood detection. In practical applications, the PRML system deals with uncertain and changing channels. Therefore, two methods are proposed to solve this problem. [0003] figure 1 It is the PRML system architecture diagram of the first method. As shown in the figure, the PRML system 10 includes an adaptive equalizer (Adaptive Equalizer) 11 and a Viterbi decoder 12 . Since the Viterbi decoder 12 is a Viterbi decoder with fixed parameters, the adaptive equalizer 11 is used to reshape the waveform of the input...

Claims

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Application Information

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IPC IPC(8): G11B20/14G11B20/18H03M1/12H03M13/23
Inventor 陈宏庆沈文仁
Owner MEDIATEK INC
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