Capacitance element and mfg method thereof

A technology of capacitive elements and manufacturing methods, which is applied in the direction of electrical components, fixed capacitance parts, capacitors, etc., can solve problems such as complex electrode structures, and achieve the effects of reducing deviation, reducing characteristic deviation, and reducing characteristic deviation

Inactive Publication Date: 2004-03-24
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] In addition, in order to prevent the diffusion of metal atoms constituting the ferroelectric thin film, a method of providing a metal oxide layer on the lower electrode is disclosed (Japanese Patent Application Laid-Open No. 5-226715), but the electrode structure is more complicated, and there are problems in practical use.

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  • Capacitance element and mfg method thereof
  • Capacitance element and mfg method thereof
  • Capacitance element and mfg method thereof

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no. 1 Embodiment approach

[0033] Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings. figure 1 11 is a Si substrate, 12 is an insulating film such as a silicon oxide film, 13 is a contact plug made of polysilicon (PS) or tungsten (W), and 14 is an oxide film. An insulating film such as a silicon film, 15 is a lower electrode made of Pt, and 16 is made of SBT (SrBi 2 Ta 2 o 9 ) composed of a ferroelectric thin film, 17 is an upper electrode composed of Pt. The film thickness of the lower electrode 15 is 50 nm, and the film thickness variation is controlled within 10%. By controlling the film thickness of the lower electrode in this way, when the ferroelectric thin film 16 is produced by the MOCVD method, it is possible to prevent the Bi metal constituting the ferroelectric thin film 16 from the Pt lower electrode 15 in the capacitive element and between the capacitive elements. Since the amount of diffusion is controlled, it is possibl...

no. 2 Embodiment approach

[0039] Hereinafter, a second embodiment of the present invention will be described in detail with reference to the drawings.

[0040] image 3 is a cross-sectional view showing the capacitive element of the present invention, in image 3 Among them, 31 is a Si substrate, 32 is an insulating film such as a silicon oxide film, 33 is a contact plug made of polysilicon (PS) or tungsten (W), 34 is an insulating film such as a silicon oxide film, and 35 is made of Pt. The lower electrode, 36 is a ferroelectric thin film made of SBT, 37 is an upper electrode made of Pt, and 38 is a concave portion with a depth of 300 nm.

[0041] image 3 The manufacturing method of the capacitive element shown is substantially the same as the method described above in FIG. 2 of the first embodiment except for a part of the process. The difference is that the concave portion 38 is formed deeper, and the lower electrode 35 does not completely fill the concave portion 38, but along the bottom portio...

no. 3 Embodiment approach

[0046] Hereinafter, a third embodiment of the present invention will be described in detail with reference to the drawings.

[0047] Figure 5 A sectional view showing a capacitive element of the present invention, in Figure 5 Among them, 41 is a Si substrate, 42 is an insulating film such as a silicon oxide film, 43 is a contact plug made of polysilicon (PS) or tungsten (W), 43a is an upper extension of the contact plug 43, and 44 is a silicon oxide film. An insulating film such as an oxide film, 45 is a lower electrode made of Pt, 46 is a ferroelectric thin film made of SBT, and 47 is an upper electrode made of Pt.

[0048] exist Figure 5 Among them, the width of the lower electrode 45 is controlled at 40 nm, and the deviation of the width is controlled within 10%. In this way, the lower electrode is not like figure 1 expand horizontally like that, but instead like Figure 5 When extending in the vertical direction in this way, the above-mentioned width of the lower ...

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Abstract

A capacitor element is composed of a lower electrode, a ferroelectric film, and an upper electrode that are formed on a substrate. In the capacitor element, the ferroelectric film is formed by a reaction rate-determining method, and the lower electrode has a thickness of not more than 100 nm, and variation of the thickness of not more than 10%. With this, a capacitor element in which the composition variation of the ferroelectric film is suppressed, and a method for producing the same, are provided.

Description

technical field [0001] The present invention relates to a capacitive element in which a ferroelectric thin film is formed by a reaction rate-determining method and a method for manufacturing the same, and more particularly to a capacitive element capable of providing a film thickness of 100 nm or less on a lower electrode with less variation in characteristics A capacitive element of a ferroelectric memory (hereinafter referred to as FeRAM) and a manufacturing method thereof. Background technique [0002] FeRAM is a non-volatile memory with the characteristics of high-speed rewriting and many times of rewriting. With the development of high integration, it is urgently required to miniaturize the storage unit, especially the longitudinal (thickness direction) and lateral direction of the capacitive elements constituting the storage unit. (Indicates the miniaturization of the horizontal direction perpendicular to the thickness direction). For miniaturization, the lower electr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/105H01G4/08H01G4/12H01L21/02H01L21/314H01L21/316H01L21/8246
CPCH01L28/90H01L21/31691H01L28/55H01G4/12H01G4/08H01L21/02271H01L21/02164H01L21/02197H01L27/105
Inventor 藤井英治伊东丰二
Owner PANASONIC CORP
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