Discrete 3780-point Fourier transformation processor system and its structure

Abstract

3780 points discrete Fourier transform processer system includes 63 points DFT module, complex multiplicator moduel, line and column crossing processor module and 60 points DFT module to be connectedin sequence according to the calculation, of which the position of each module in the abovelisted modules can be interchangeable. The processor is structuralized by two modules in front and back to share one FPGA chip and two FPGA chips being connected by two-part RAM. According to the calculation and connecting sequence 63 point DFT module will be formed by 7 point (or 9 point) DFT module-label mapping module under 63 point DFT prime factor calculation-9 point (or 7 point) DFT module, 60 point DFT module can be also decomposed similarly as 3X20, 4X15, 5X12 point DFT as well as 12 point and 15 point DFT module can be decomposed as 3X4, 3X5 point DFT module. The whole 3780 point DFT processor needs only two FPGA chips of three hundred thousand gates for saving a great deal of the cost.

Description

technical field [0001] A 3780-point DFT (discrete Fourier transform) processor system and its structure belong to the hardware implementation of DFT fast algorithm, and particularly relate to the technical field of multi-carrier signal DFT processor system. Background technique [0002] The invention relates to the application of DFT in the orthogonal frequency division multi-carrier modulation and demodulation technology in the communication technology. In order to realize OFDM, the quadrature phase-modulated single-carrier baseband signal needs to be subjected to inverse discrete Fourier transform (IDFT) to obtain the sub-carriers used for OFDM multi-carrier modulation. During demodulation, the multi-carrier signal is subjected to discrete Fourier transform to obtain a single-carrier baseband signal modulated by quadrature phase, and then the symbol of information is obtained by quadrature phase demodulation. According to the theory of digital signal processing, DFT can b...

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Problems solved by technology

The 3780-point DFT module it uses is implemented in the prototype with three FPGAs of 400,000 gates. The hardware resource consumption is large and the cost is high. The reason is that the 3780-point DFT is calculated in this way: first, the 3780-point DFT is decomposed into 3-point DFT and 1260-point DFT are synthesized through 3×1260 row-column interleaving processing and twiddle factor multiplication; 1260-point DFT is decomposed into 3-point DFT and 420-point DFT, and 3×420 row-column interleaving processing and twiddle factor The 420-point DFT is decomposed into 4-point DFT and 35-point DFT, which are synthesized through 4×35 row-column interleaving processing and multiplication of rotation factors; the 35-point DFT is decomposed into 5-point DFT and 7-point DFT, and passed 5×7 row-column interleaving processing and twiddle factor multiplication are synthesized

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