Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Frame synchronized parallel scrambler and parallel de-scrambler

A technology of frame synchronization and synchronous digital series, applied in electromagnetic wave transmission systems, digital transmission systems, electrical components, etc., can solve problems such as complex circuit structure, increased power consumption, and reduced reliability, and achieve simple circuit structure, stable and reliable operation , The effect of reducing the power consumption of the circuit

Inactive Publication Date: 2007-03-21
XIAN UNIV OF POSTS & TELECOMM
View PDF1 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] Because the circuit structure of the parallel scrambling code is more complex, it takes up more resources when it is implemented with a field programmable gate array (FPGA) device, and it takes

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Frame synchronized parallel scrambler and parallel de-scrambler
  • Frame synchronized parallel scrambler and parallel de-scrambler
  • Frame synchronized parallel scrambler and parallel de-scrambler

Examples

Experimental program
Comparison scheme
Effect test
No Example Login to View More

PUM

No PUM Login to View More

Abstract

Frame simultaneous parallel scrambler and parallel de-scrambler in transmission system of SDH are contained in timing clock simultaneous generated and parallel feedback shift register of 16 bits pseudo random sequence respectively. The feedback shift register is composed of shift register including 16 pieces of D trigger, and feedback network composed of 16 pieces of exclusive-or gate. Clock ends of D15-D0 of D trigger are connected to same clock signal. Setting ends of D15-D9 and D2 as well as zero setting ends of D8-D3 and D1, D0 are connected to frame synchronizing pulse. Thus, at time of staring frame, D15-D0 of the feedback shift register is reset to 1111111000000100. After bit-oriented exclusive-or between parallel scrambler and input signal, scrambled signal output is formed. After bit-oriented exclusive-or between de-scrambler and signal, de-scramble is realized so as to form signal output. Features are: simple structure, small power consumption, and high reliability.

Description

technical field [0001] The present invention relates to a coding and decoding circuit of a transmission system, to be precise, relates to a frame synchronous parallel scrambler and a parallel descrambler for a Synchronous Digital Hierarchy (SDH) transmission system, which belongs to the coding control of transmission digital information Circuit technology field. Background technique [0002] Synchronous Digital Hierarchy (SDH, Synchronous Digital Hierarchy) is a digital communication system in an optical fiber communication system, and it is also a set of new international communication standards. The basis of the SDH concept is the Synchronous Optical Network (SONET) proposed by the Bell Institute of Communication Technology in the United States. The Consultative Committee for International Telephony and Telegraphy (CCITT, now ITU-T) accepted the SONET concept in 1988 and renamed it SDH, making it suitable for both optical fiber and microwave and satellite transmission. G...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H04B10/02H04J3/16H04L1/00
Inventor 张德慧蒋林曾泽沧袁立行
Owner XIAN UNIV OF POSTS & TELECOMM
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com