Directly connected interface unit for memory test machine and integrated circuit sorter

Abstract

The directly connected interface unit for memory test machine and integrated circuit sorter includes main base board, printed circuit board, the first position aligning structure and the first fixing structure. The main base board has the second position aligning structure and the second fixing structure and is set on integrated circuit sorter. The main base board has upper edge lower than the feeding jog dial area and one opening to expose the distributor area. The printed circuit board is set on the memory test machine. The first position aligning structure set on the memory test machine is suitable for embedding with the second position aligning structure. The first fixing structure set on the memory test machine is suitable for connection with the second fixing structure in detachable mode.

Description

technical field [0001] The present invention relates to a direct mount interface device, and in particular to a direct mount interface device for a memory tester (Memory tester) and an integrated circuit sorter (IC handler). Background technique [0002] In the manufacturing process of integrated circuits, any mechanical equipment, process parameters, process environment and other factors not listed may have a negative impact on the integrated circuit process, resulting in manufacturing defects. However, for products supplied to consumers, the problem of such manufacturing defects can be minimized through prior testing and classification. [0003] In the method of testing and classifying integrated circuits, as shown in FIG. 1 , a memory testing machine 100 and an integrated circuit classifying machine 102 are connected to each other for testing and classifying integrated circuits. Generally speaking, the testing and sorting method is, for example, placing the integrated ci...

AI Technical Summary

Problems solved by technology

[0010] Since the above-mentioned power supply and grounding of the integrated circuit under test are transmitted through the power line, they are susceptible to external noise interference, resulting in incorrect test results.

[0011] Moreover, the signal is transmitted through the coaxial isolated signal line, and the path it passes through is long, which can easily cause delays in the timing of the signal reaching the pins of the integrated circuit, making the test results incorrect

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