Buffer programming method based on blank region redistribution
A technology of buffer and blank area, applied in the field of BBL
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment Construction
[0073] The present invention can be implemented under different layout plans / layout representations based on rectangular divisions (that is to say, this type of layout representation divides the chip into rectangular areas whose number is greater than or equal to the number of modules, and each rectangular area has at most one module) . This part adopts the layout result represented by CBL as an example of the present invention, and adopts the Elmore time delay model as the model of time delay calculation. combine figure 2 The flowchart of using the method of the present invention to carry out floorplanning based on redistribution of white space. Table 1 is the definition of some variables.
[0074] r
Wire resistance per unit length (Ω / μm)
c
Line capacitance per unit length (fF / μm)
T b
Buffer Intrinsic Latency (ps)
C b
Buffer Input Capacitance (fF)
R b
Buffer output resistance (Ω)
R d...
PUM
Abstract
Description
Claims
Application Information
- R&D Engineer
- R&D Manager
- IP Professional
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com