High-performance grid nitride ROM structure

Abstract

The present invention discloses a high-performance gate nitride read-only memory structure, said structure contains tunnel oxide layer on the base material, an amorphous silicone layer on the tunnel oxide layer, the polycrystalline silicone germanium layer on the amorphous silicone layer, then inner polycrystalline silicone dielectric layer on the polycrystalline silicone germanium layer and finally polycrystalline silicone layer on the inner polycrystalline silicone dielectric layer.

Description

Field of invention: [0001] The invention relates to a structure of a semiconductor element, in particular to a structure of a high-efficiency gate nitride read-only memory. Background of the invention: [0002] A semiconductor device usually includes a plurality of independent components formed on or in a substrate. For example, like the existing Figure 1A As shown, a memory device such as flash memory 100 includes one or more memory arrays 102 and surrounding areas 104 on a substrate 106 . Typically the memory array 102 consists of at least one single MXN array, substantially typically of the same floating gate type memory cell, and the surrounding area 104 contains input / output circuits and circuits for selectively specifying cell addresses (e.g., for link selection The source, gate and drain of the address of a specific unit affect the operation of the specified unit with a set voltage or impedance, such as programming, reading or clearing). [0003] The memory cells i...

AI Technical Summary

Problems solved by technology

Undesirably high doping heights result in an uneven surface between the floating gate and tunnel oxide, resulting in high local electric fields, low oxide dielectric strength, and program / erase endurance cycling issues

[0007] Disadvantages of the prior art are that the polysilicon gate has poor function and low doping active area, low reliability between polysilicon layer / oxide layer or polysilicon germanium layer / silicon dioxide layer interface, and low gate oxide density

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