Method and device for eliminating interruption false triggering of multi-core DSP (Digital Signal Processor)

Abstract

The invention provides a method and a device for eliminating interruption false triggering of a multi-core DSP (Digital Signal Processor). The method comprises the steps that an interrupt label Ln corresponding to a core n is set, n = 1,..., N-1, and N is the number of cores in the multi-core DSP; setting Ln = 1, n = 1,..., N-1 in an interrupt service program of the core 0; reading the value of Ln at the beginning of the interrupt service program of the core n, if Ln is equal to 1, resetting Ln, and executing subsequent program codes; if Ln = 0, directly exiting the interrupt program; n = 1, 2,..., N-1. According to the method, the problem of repeated interruption false triggering between multi-core DSP embedded software cores is effectively solved, when a certain core generates repeated interruption false triggering, an interruption service program of the core is quitted immediately, false triggering is not generated on a subsequent core any more, the core program and other core programs can run stably, and the reliability of the core program is improved. And the high reliability of the operation of the multi-core DSP embedded software system is ensured.

Description

technical field [0001] The invention belongs to the technical field of computer interrupts, and in particular relates to a method main device for eliminating false triggering of multi-core DSP interrupts. Background technique [0002] At present, the application of multi-core computers is more and more extensive. For example, the internal navigation computer board of the positioning and directional aiming system (hereinafter referred to as the fixed aiming system) adopts a multi-core DSP (TMS320C6674) and has 4 cores, which are called core 0, core 1, core 2 and core 3 respectively. Each core runs its own software program, and the interaction of data and instructions between the cores is generally processed by means of an inter-core interrupt. The sequence of inter-core interrupts starts from core 0, core 0 triggers core 1, core 1 triggers core 2, and core 2 triggers core 3, of which core 0 is triggered by the timer interrupt every 1ms, which ensures that there will be no re...

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Problems solved by technology

The sequence of inter-core interrupts starts from core 0, core 0 triggers core 1, core 1 triggers core 2, core 2 triggers core 3, and core 0 is triggered by a timer interrupt every 1ms, which can ensure that there will be no repeated errors. However, each core in the subsequent core 1, core 2, and core 3 may experience repeated false triggering of interrupts, causing other cores to follow the false triggering phenomenon when responding to inter-core interrupts, making the system software run unstable; In severe cases, it will cause some core software to crash

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